DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 102 3
A. Claims 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2005/0145987 (“Okuda”). 3
III. Claim Rejections - 35 USC § 103 5
A. Claims 1, 2, 11, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Okuda. 5
IV. Allowable Subject Matter 9
V. Pertinent Prior Art 12
Conclusion 13
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2005/0145987 (“Okuda”).
With regard to claim 18, Okuda discloses, generally in Fig. 15,
18. A capacitor [in the “capacitor forming region 22” (¶ 31)] comprising:
[1] a first interconnect level [any one or more of M1, M2, and M3] above a substrate 1 [¶¶ 31, 33];
[2] a first plurality of metal layers 11 in the first interconnect level [¶¶ 33, 74];
[3] a second interconnect level M4 [¶ 74] above the first interconnect level [any one or more of M1, M2, and M3];
[4] a second plurality of metal layers 57 in the second interconnect level M4, wherein the metal layers 74 in the second plurality of metal layers are electrically floating [¶ 73: “a plurality of floating interconnections 57 spaced from each other are formed at a position in M4 layer sandwiched between interconnections 12 at both ends (i.e., at a position surrounded by a chain double-dashed line 56).”];
[5] a third interconnect level M5 above the second interconnect level M4 [¶¶ 73-74]; and
[6] a third plurality of metal layers 38 in the third interconnect level M5 [¶¶ 73-74].
With regard to claim 19, Okuda further discloses,
19. The capacitor of claim 18, wherein the metal layers 57 in the second plurality of metal layers 57 are not connected to a voltage source or a current source [because “floating”, by definition, lacks a voltage source or current source (¶ 73)].
It is held, absent evidence to the contrary, that because the term “electrically floating”, by definition, lacks a voltage source or current source to the component that is electrically floating, that there is no voltage source or current source connected to the electrically floating metal layers 57 in the metal level M4. As such, the burden of proof is shifted to Applicant to prove the contrary. (See MPEP 2112(I)-(V).)
With regard to claim 20, Okuda further discloses,
20. The capacitor of claim 18, wherein the second interconnect level M4 is immediately above the first interconnect level M3 and immediately below the third interconnect level M5.
III. Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1, 2, 11, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Okuda.
With regard to claim 1, the embodiment shown in Fig. 15 of Okuda (i.e. the “Seventh Embodiment” [¶¶ 72-74]) discloses,
1. A capacitor comprising:
[1] a first interconnect level [any one or more of M1, M2, and M3] above a substrate 1;
[2] a first plurality of metal layers 11 in the first interconnect level;
[3] a second interconnect level M4 above the first interconnect level;
[4] a second plurality of metal layers 57 in the second interconnect level M4, wherein the metal layers 57 in the second plurality of metal layers 57 are electrically floating [¶ 73: “a plurality of floating interconnections 57 spaced from each other are formed at a position in M4 layer sandwiched between interconnections 12 at both ends (i.e., at a position surrounded by a chain double-dashed line 56).”];
[5] … [not taught] …
[6] a fourth interconnect level M5 above the third interconnect level M4; and
[7] a third plurality of metal layers 38 in the fourth interconnect level M5.
With regard to claim 1, the embodiment shown in Fig. 18 of Okuda (i.e. the “Tenth Embodiment” [¶¶ 81-83]) discloses,
1. A capacitor comprising:
[1] a first interconnect level M2 above a substrate 1;
[2] a first plurality of metal layers 11 in the first interconnect level M2;
[3] a second interconnect level M3 above the first interconnect level M2;
[4] a second plurality of metal layers 11 in the second interconnect level M3, …
[5] a third interconnect level M4 above the second interconnect level, the third interconnect level is devoid of any metal layers [¶ 82: “no interconnections are provided in a position in M4 layer sandwiched between interconnections 12 at both ends (i.e., at a position surrounded by a chain double-dashed line 63), and the position is filled with insulating layer 5”];
[6] a fourth interconnect level M5 above the third interconnect level M4; and
[7] a third plurality of metal layers 38 in the fourth interconnect level M5.
With regard to features [4] and [5] of claim 1, the embodiment shown in Fig. 15 does not include an metal level devoid of any metal layers in the capacitor forming region 22, while the embodiment shown in Fig. 18 does not include a metal level having a plurality of electrically floating metal lines.
However, Okuda states that the embodiments can be combined to achieve the combined effects of the embodiments:
[0110] The embodiments described above may be combined as appropriate to form the semiconductor device in accordance with the present invention, and in that case, the effects similar to those described in the combined embodiments can be obtained. For example, when the configuration satisfying the occupied area ratio shown in FIG. 22 is applied to the semiconductor device shown in FIG. 13, the effects described in the fifth and the fourteenth embodiments can be achieved.
(Okuda: ¶ 110; emphasis added)
With regard to each of the seventh (Fig. 15) and tenth (Fig. 18) embodiments, Okuda teaches that the purpose is to reduce the parasitic capacitance between the interconnection 11 and the interconnection 38, thereby “a circuit using interconnection capacitance 8 can be implemented with higher accuracy” (¶¶ 74, 83).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the seventh and tenth embodiments to thereby provide
[4] a second plurality of metal layers 57 in the second interconnect level M4, wherein the metal layers 57 in the second plurality of metal layers 57 are electrically floating [as in Fig. 15]
[5] a third interconnect level above the second interconnect level M4, the third interconnect level [hereafter “M5'”] is devoid of any metal layers [as shown in Fig. 18]
because Okuda suggests combining embodiments to achieve combined effects (¶ 110, supra). The original metal level M5 shown in Figs. 15 and 18 would become an additional metal level M6 over the new metal level M5'.
The benefit, before the effective filing date of the claimed invention, would be to further reduce the parasitic capacitance between the interconnections 11 and interconnections 38 versus either of the means in the seventh (Fig. 15) and tenth (Fig. 18) embodiments.
This is all of the limitations of claim 1.
With regard to claim 2,
2. The capacitor of claim 1, wherein the metal layers 57 in the second plurality of metal layers M4 are not connected to a voltage source or a current source.
See discussion under claim 19, above, which is applied here.
With regard to claim 11, the combination of the seventh (Fig. 15) and tenth (Fig. 18) embodiments of Okuda, as explained under claim 1, further teaches,
11. A capacitor comprising:
[1] a first interconnect level M3 above a substrate 1;
[2] a first plurality of metal layers 11 in the first interconnect level M3;
[3] a second interconnect level M4 above the first interconnect level M3;
[4a] a second plurality of metal layers 57 in the second interconnect level,
[4b] the second plurality of metal layers 57 includes a first position metal layer [leftmost of 57 in Fig. 15] and a last position metal layer [rightmost of 57 in Fig. 15],
[4c] wherein the metal layers 57 in the second plurality of metal layers 57 are not connected to a voltage source or a current source [because they are electrically floating (¶ 73, supra)];
[5a] a third interconnect level [M4 of Fig. 18, which is new M5' of the combination of the embodiments in Figs. 15 and 18, as explained under claim 1] above the second interconnect level M4,
[5b] the third interconnect level M5' includes a metal-less region 63 that is devoid of any metal layers [as shown in Fig. 18 (¶ 82)],
[5c] the metal-less region 63 has opposing peripheral sides bounded by at least a vertical plane taken from a distal top edge of the first position metal layer in the second plurality of metal layers and a vertical plane taken from at a distal top edge of the last position metal layer in the second plurality of metal layers [because the interconnections 12 in all of the metal levels define the end of the capacitor forming region 22, as shown in each of Figs. 15 and 18];
[6] a fourth interconnect level [M5 in Figs. 15 and 18 which becomes new metal level M6 in the combination of the embodiments in Figs. 15 and 18, as explained under claim 1] above the third interconnect level M5'; and
[7] a third plurality of metal layers 38 in the fourth interconnect level M6.
With regard to claims 16 and 17, the combination of the seventh (Fig. 15) and tenth (Fig. 18) embodiments of Okuda, as explained under claim 1, further teaches,
16. The capacitor of claim 11, wherein
[1] the third plurality of metal layers 38 includes a first position metal layer [leftmost 38 in Fig. 18] and a last position metal layer [rightmost 38 in Fig. 18],
[2] the peripheral sides of the metal-less region 63 are bounded by at least a vertical plane taken from a distal top edge of the first position metal layer [leftmost 38 in Fig. 18] in the third plurality of metal layers 38 and a vertical plane taken from a distal top edge of the last position metal layer [rightmost 38 in Fig. 18] in the third plurality of metal layers 38, and
[3] wherein the metal-less region 63 is aligned vertically between the second plurality of metal layers 57 and the third plurality of metal layers 38 [as shown in Figs. 15 and 18].
17. The capacitor of claim 16, wherein
[1] each metal layer 38 in the third plurality of metal layers [i.e. new M6, supra] has a bottom surface,
[2] each metal layer 57 in the second plurality of metal layers M4 has a top surface and a bottom surface,
[3] each metal layer 11 in the first plurality of metal layers M3 has a top surface, and
[4] wherein a vertical displacement between the bottom surface of each metal layer 38 in the third plurality of metal layers 38 and the top surface of each metal layer 57 in the second plurality of metal layers 57 is larger than a vertical displacement between the bottom surface of each metal layer in the second plurality of metal layers and the top surface of each metal layer in the first plurality of metal layers [because of the additional space resulting from the no-interconnection region 63 of Fig. 18, i.e. the new M5' of combined Figs. 15 and 18, above the floating interconnections 57 in Fig. 15.
IV. Allowable Subject Matter
Claims 3-10 and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 reads,
3. The capacitor of claim 2,
[1] wherein each metal layer in the third plurality of metal layers [of the fourth interconnect layer] is aligned above each metal layer in the first plurality of metal layers along a vertical direction, and
[2] wherein each metal layer in the third plurality of metal layers has an opposite polarity to each respective metal layer in the first plurality of metal layers aligned along the vertical direction.
With regard to claim 3, the combination of the seventh (Fig. 15) and tenth (Fig. 18) embodiments, as explained under claim 1, further teaches,
3. The capacitor of claim 2,
[1] wherein each metal layer 38 in the third plurality of metal layers [i.e. effectively the new metal level M6, i.e. the claimed the “fourth interconnect layer”] is aligned above each metal layer 11 in the first plurality of metal layers 11 [in M3] along a vertical direction [as shown in Figs. 15 and 18], and
[2] wherein each metal layer 38 in the third plurality of metal layers 38 has an opposite polarity to each respective metal layer in the first plurality of metal layers 11 [in M3] aligned along the vertical direction.
Okuda states that all of the interconnections 38 (38n and 38m in Fig. 10) are fixed to ground (¶¶ 62-63), while each of the interdigitated interconnections 11m and 11n are at different potentials in order to form the capacitance (¶ 38; Fig. 6). Therefore, Okuda does not disclose the limitations of feature [2] of claim 3.
The prior art does not reasonably teach or suggest—in the context of claim 3—the limitation “wherein each metal layer in the third plurality of metal layers has an opposite polarity to each respective metal layer in the first plurality of metal layers aligned along the vertical direction”.
Claims 4-10 would be allowable at least for including the same allowable limitation by depending from claim 3, either directly or indirectly.
Claim 12 reads,
12. The capacitor of claim 11, further comprising
[1] an anode and a cathode,
[2a] wherein the first plurality of metal layers includes a first set of metal layers connected to the anode and a second set of metal layers connected to the cathode,
[2b] the first set of metal layers is interdigitated with the second set of metal layers, and
[3a] wherein the third plurality of metal layers include a third set of metal layers connected to the anode and a fourth set of metal layers connected to the cathode,
[3b] the third set of metal layers is interdigitated with the fourth set of metal layers.
With regard to claim 12, the combination of the seventh (Fig. 15) and tenth (Fig. 18) embodiments, as explained under claims 1 and 11, further teaches,
12. The capacitor of claim 11, further comprising
[1] an anode and a cathode [not shown but inherently present because 11m and 11n are at different potentials (¶ 38) in order to have a capacitance 8 in the capacitor forming region 22],
[2a] wherein the first plurality of metal layers 11 includes a first set of metal layers [e.g. 11m] connected to the anode and a second set of metal layers [e.g. 11n] connected to the cathode [¶ 38: “Thus, by providing a potential difference between interconnections 11m and 11n, an interconnection capacitance 8 using insulating layer 5 as a dielectric layer is formed between interconnections 11m and 11n adjacent to each other in each plane 21 defined in M1 layer to M4 layer.”],
[2b] the first set of metal layers 11m is interdigitated with the second set of metal layers 11n [¶¶ 35, 38, Fig. 6], and
[3a] wherein the third plurality of metal layers 38 include a third set of metal layers 38n … and a fourth set of metal layers 38n …
[3b] the third set of metal layers 38m is interdigitated with the fourth set of metal layers 38n [¶ 62; Fig. 10].
As explained under claim 3, above, Okuda states that all of the interconnections 38 (38n and 38m in Fig. 10) are fixed to ground (¶¶ 62-63) and not, consequently, not connected to the anode and cathode, respectively. Therefore, Okuda does not disclose the limitations of feature [3a] of claim 12.
The prior art does not reasonably teach or suggest—in the context of the claim 12—the “wherein the third plurality of metal layers include a third set of metal layers connected to the anode and a fourth set of metal layers connected to the cathode”.
Claims 13-15 would be allowable at least for including the same allowable limitation by depending from claim 12, either directly or indirectly.
V. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2013/0113077 (“Woo”) is cited for teaching a capacitor built in the interconnect of an integrated circuit chip including floating interconnect lines F among the cathode lines C and anode lines A, but not as configured as required by any of the instant claims. (See Figs. 2, 3, and 5, and the associated text.)
US 2014/0273394 (“Roehner”) is cited for teaching a capacitor (Fig. 9C) built in the interconnect of an integrated circuit chip including floating interconnect lines 50 among the cathode lines 40 (i.e. – in Fig. 9B) and anode lines 30 (i.e. + in Fig. 9B), but not as configured as required by any of the instant claims. (See Figs. 9A-9C and associated text, at least ¶¶ 74-75.)
Conclusion
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814