Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because the contact capping layer 138 is represented in figure 4f having the same pattern as the source/drain contact 118’. The source/drain contact 118 is described in Applicant’s instant specification as being formed of metal (0080), whereas the contact capping layer 138 is described in Applicant’s instant specification as being formed of an oxide (0099). Therefore, these features must be represented by different patterns in the figure. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 13 is objected to because of the following informalities: In claim 13, “further comprising and the method further comprising” should read “further comprising”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, 9, and 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US Patent Pub 20200373331 A1).
Regarding Claim 1, Kim teaches a method for forming a semiconductor device, the method comprising:
forming a device structure on a substrate, the device structure comprising a fin structure comprising a pair of source/drain bodies and a channel region between the pair of source/drain bodies, (Fig. 2B shows the formation the device on substrate 100. Fig. 18 shows the fin structures FA comprising a pair of source/drain bodies (Fig. 19B, source/drain regions 130 on either side of the fin structure FA. Paragraph 0022 teaches the fin is acting as a channel under the gate structures GS),
the channel region comprising at least one channel layer (Fig 19C shows the channel region comprises the channel layer, which is the fin structure FA),
and the device structure further comprising a gate structure extending across the channel region of the fin structure (Fig. 19C, gate structure GL);
forming a metal layer over the source/drain bodies (Fig. 19B, metal layer CP1 and VC formed over the source/drain bodies. Paragraph 0110 teaches CP1 /VC can be formed of metal and can be formed concurrently);
etching the metal layer to define a first source/drain contact and a second source/drain contact on the source/drain bodies (Fig. 19B, a hole CH1 is etched into metal layer CP1, indicating an etching step took place and creating a first source/drain contact (left side of 130/CP1) and second source/drain contact (right side of 130/CP1);
and depositing an interlayer dielectric layer over the gate structure, the first source/drain contact, and the second source/drain contact (Fig. 19B, interlayer dielectric layer 128 and 142).
Regarding Claim 8, Kim teaches the method according to claim 1, wherein the gate structure comprises a sacrificial gate and the method further comprises, subsequent to forming the interlayer dielectric layer, removing the sacrificial gate to form a gate trench and forming a replacement metal gate in the gate trench (An alternative interpretation of Kim would have the gate structure be sacrificial gate D14 and the interlayer dielectric layer be D16 formed upon D14. Paragraphs 0114 and 0115 teach that the sacrificial gate D14 is removed and replaced by a replacement metal gate GL. Paragraph 120 teaches GL is metal).
Regarding Claim 9, Kim teaches the method according to claim 1, wherein the device structure further comprises a buried wiring line formed in a trench extending alongside the fin structure and capped by an insulating wiring capping layer, wherein the method further comprises forming a via hole in the insulating wiring capping layer to expose an upper surface of the buried wiring line, and subsequently forming the metal layer, wherein the metal layer fills the via hole and wherein the metal layer is etched such that the first source/drain contact is formed in contact with the buried wiring line and one of the source/drain bodies (Fig. 17B, buried wiring line 150 located in a trench extending alongside the fin structures FA and capped by insulating wiring capping layer 112c. Fig. 19B and paragraph 0109 teaches the formation of via hole VH penetrating 112c and the subsequent formation of the metal layer CP1/VC. Paragraph 0109 and 110 teach the CP1/VC fills the via hole. The metal layer is etched to form hole CH1, defining first source/drain contact (left side of 130/CP1), which is formed in contact with buried wiring line 150 and the left source/drain body 150).
Regarding Claim 15, Kim in view of Wang teaches the method according to claim 9, wherein the buried wiring line is a buried power rail (Kim, Fig. 21 and paragraph 0127 teach buried wiring line 150 is a buried power rail).
Regarding Claim 16, Kim teaches the method according to claim 1,
wherein the device structure comprises a plurality of parallel fin structures (Fig. 19, plurality of fin structures FA),
each of the parallel fin structures comprising a number of pairs of source/drain bodies and a channel region between each pair of source/drain bodies (Fig. 19B, source/drain regions 130 on either side of the fin structure FA. Paragraph 0022 teaches each fin is acting as a channel under the gate structures GS and that channels are formed on the opposite side walls of each fi-type active area FA),
the device structure further comprising a plurality of parallel gate structures spaced apart by gaps and extending transverse to and across the parallel fin structures such that each channel region is overlapped by a respective one of the parallel gate structures (Fig. 19A, plurality of gate structures GS which are spaced apart and extend transverse to and across parallel fin structures FA such that each channel region is overlapped by one of the gate structures)
wherein the metal layer is formed to fill the gaps between the parallel gate structures and subsequently etched to define source/drain contacts on the source/drain bodies in each gap (Fig. 19A, metal layer CP1 fills in gaps between the parallel gate structures. Fig. 19B shows the etched hole CH1 which defines the source/drain contacts 130/CP1 left side and 130/CP1 right side).
Regarding Claim 17, Kim teaches the method according to claim 16, wherein forming the metal layer comprises depositing metal over the device structure to completely fill the gaps between the parallel gate structures, and recessing the metal to expose an upper surface of the gate structure (Fig. 19B, the gaps between the fins after formation of 130 are filled in by deposited metal layer CP1. Any gap below 130 had been filled by 126).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 1, 8, 9, and 15-17 above, and further in view of Wang et al. (US Patent Pub 20140084340 A1, hereafter referred to as Wang 340).
Regarding Claim 2, Kim teaches the method according to Claim 1.
Kim fails to teach the method wherein forming the metal layer comprises depositing metal over the device structure to cover and surround the gate structure and the source/drain bodies.
However, Wang 340 teaches a method of forming a finfet device wherein forming the metal layer comprises depositing metal over the device structure to cover and surround the gate structure and the source/drain bodies (Wang 340, Fig. 11, metal layer 228 is deposited over the device structure to cover and surround the gate structure 210 and source/drain bodies 208).
It would have been obvious to one or ordinary skill in the art at the time of invention to incorporate the teachings of Wang 340 into the method of Kim wherein forming the metal layer comprises depositing metal over the device structure to cover and surround the gate structure and the source/drain bodies. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of filling the openings within the device structure during the fabrication process (Wang 340, paragraph 0036).
Regarding Claim 3, Kim in view of Wang 340 teaches the method according to claim 2, wherein forming the metal layer further comprises recessing the metal to expose an upper surface of the gate structure (Wang 340, Fig. 12. Paragraph 0037 teaches recessing the metal layer 228, which in turn exposes an upper surface of gate structure 210).
Regarding Claim 4, Kim in view of Wang 340 teaches the method according to claim 1, wherein the metal layer comprises a metal liner sub- layer and a metal fill sub-layer over the metal liner sub-layer (Wang 340, paragraph 0036 teaches the metal layer 228 may be multi-layered, comprising a metal liner sub-layer and a metal fill sub-layer. The metal fill sub-layer may be over the metal liner sub layer).
Claim(s) 5-7 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 1, 8, 9, and 15-17 above, and further in view of Tsai et al. (US Patent Pub 20200035605 A1).
Regarding Claim 5, Kim teaches the method of claim 1.
Kim fails to teach the method further comprising recessing the interlayer dielectric layer to expose an upper surface of the first source/drain contact and the second source/drain contact.
However, Tsai teaches a method of fabricating a finfet device comprising recessing the interlayer dielectric layer to expose an upper surface of the first source/drain contact and the second source/drain contact (Tsai, Fig. IG, IH, and paragraph 0044 teach the recessing of interlayer dielectric layer 138/140, exposing an upper surface of the first and second source/drain contacts 134S and 134D).
It would have been obvious to one or ordinary skill in the art at the time of invention to incorporate the teachings of Tsai into the method of Kim by recessing the interlayer dielectric layer to expose an upper surface of the first source/drain contact and the second source/drain contact. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of exposing the source/drain contacts to form further connecting structures on (Tsai, paragraph 0044).
Regarding Claim 6, Kim in view of Tsai teaches the method according to claim 5, further comprising etching back the first source/drain contact and the second source/drain contact to form recessed source/drain contacts (Tsai, paragraph 0045 teaches etching back the source/drain contacts 134S/142S and 134D/142D (142S and 142D are now included after their formation as they are electrically connected to the original source/drain contacts and are contact structures themselves) using a CMP process to planarize the source/drain contacts to remove excess material. Thus, the source/drain contacts are recessed).
Regarding Claim 7, Kim in view of Tsai teaches the method according to claim 6, further comprising forming an insulating contact capping layer on the first source/drain contact and the second source/drain contact (Tsai, Fig. 1J, insulating capping layer 148 on the first and second source/drain contacts 134S/142S and 134D/142D).
Regarding Claim 18, Kim teaches a method for forming a semiconductor device, the method comprising:
forming a device structure on a substrate, the device structure comprising a fin structure comprising a pair of source/drain bodies and a channel region between the pair of source/drain bodies (Fig. 2B shows the formation the device on substrate 100. Fig. 18 shows the fin structures FA comprising a pair of source/drain bodies (Fig. 19B, source/drain regions 130 on either side of the fin structure FA. Paragraph 0022 teaches the fin is acting as a channel under the gate structures GS),
the channel region comprising at least one channel layer (Fig 19C shows the channel region comprises the channel layer, which is the fin structure FA),
and the device structure further comprising a gate structure extending across the channel region of the fin structure (Fig. 19C, gate structure GL);
forming a metal layer over the source/drain bodies (Fig. 19B, metal layer CP1 and VC formed over the source/drain bodies. Paragraph 0110 teaches CP1 /VC can be formed of metal and can be formed concurrently);
and etching the metal layer to define a first source/drain contact and a second source/drain contact on the source/drain bodies (Fig. 19B, a hole CH1 is etched into metal layer CP1, indicating an etching step took place and creating a first source/drain contact (left side of 130/CP1) and second source/drain contact (right side of 130/CP2),
and depositing an interlayer dielectric layer over the gate structure the first source/drain contact, and the second source/drain contact (Fig. 19B, interlayer dielectric layer 128 and 142).
Kim fails to teach the method wherein the interlayer dielectric layer is recessed to expose an upper surface of the first source/drain contact and the second source/drain contact.
However, Tsai teaches a method of forming a finfet device wherein the interlayer dielectric layer is recessed to expose an upper surface of the first source/drain contact and the second source/drain contact (Tsai, Fig. IG, IH, and paragraph 0044 teach the recessing of interlayer dielectric layer 138/140, exposing an upper surface of the first and second source/drain contacts 134S and 134D).
It would have been obvious to one or ordinary skill in the art at the time of invention to incorporate the teachings of Tsai into the method of Kim by recessing the interlayer dielectric layer to expose an upper surface of the first source/drain contact and the second source/drain contact. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of exposing the source/drain contacts to form further connecting structures on (Tsai, paragraph 0044).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Tsai as applied to claims 5-7 and 18 above, and further in view of Wang et al. (US Patent Pub 20140084340 A1, referred to as Wang 340).
Regarding Claim 19, Kim in view of Tsai teaches the method according to claim 18.
Kim in view of Tsai fails to teach the method wherein forming the metal layer comprises depositing metal over the device structure to cover and surround the gate structure and the source/drain bodies.
However, Wang 340 teaches a method of fabricating a finfet semiconductor device wherein forming the metal layer comprises depositing metal over the device structure to cover and surround the gate structure and the source/drain bodies (Wang 340, Fig. 11, metal layer 228 is deposited over the device structure to cover and surround the gate structure 210 and source/drain bodies 208).
It would have been obvious to one or ordinary skill in the art at the time of invention to incorporate the teachings of Wang 340 into the method of Kim in view of Tsai wherein forming the metal layer comprises depositing metal over the device structure to cover and surround the gate structure and the source/drain bodies. The ordinary artisan would have been motivated to modify Kim in view of Tsai in the manner set forth above for at least the purpose of filling the openings within the device structure during the fabrication process (Wang 340, paragraph 0036).
Regarding Claim 20, Kim in view of Tsai and Wang 340 teaches the method according to claim 19, wherein forming the metal layer further comprises recessing the metal to expose an upper surface of the gate structure (Wang 340, Fig. 12. Paragraph 0037 teaches recessing the metal layer 228, which in turn exposes an upper surface of gate structure 210).
Claim(s) 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 1, 8, 9, and 15-17 above, and further in view of Fan et al. (US Patent Pub 20200335401 A1).
Regarding Claim 10, Kim Teaches the method according to claim 9, wherein the method teaches the formation of a via hole as well as the source/drain structures and insulating wiring capping layer.
Kim fails to teach the method wherein forming the via hole comprises forming a temporary process layer over then underlying device structure.
However, Fan teaches a method of forming a finfet semiconductor device wherein forming the via hole comprises forming a temporary process over the underlying device structure (Fan, Fig. 6 teaches temporary process layer 602 over the device structure as part of the via hole 610 formation process).
It would have been obvious to one or ordinary skill in the art at the time of invention to incorporate the teachings of Fan into the method of Kim wherein forming the via hole comprises forming a temporary process layer over the source/drain bodies and the insulating wiring capping layer. The ordinary artisan would have been motivated to modify Kim in the manner set forth above for at least the purpose of using known fabrication operations to pattern and etch the temporary process layer for the formation of via holes (Fan, paragraph 0043).
Regarding Claim 11, Kim in view of Fan teaches the method according to claim 10, further comprising etching a via opening in the temporary process layer (Fan, Fig. 6 and paragraph 0043 teaches the etching of via opening 610 into temporary process layer 602).
Regarding Claim 12, Kim in view of Fan teaches the method according to claim 11, further comprising transferring the via opening in the temporary process layer into the insulating wiring capping layer (Fan, paragraph 0043 teaches the temporary process layer 602 is used to process the layers below it up to the source/drain regions. This would include the insulating wiring capping layer of Kim).
Regarding Claim 13, Kim in view of Fan teaches the method according to claim 12, further comprising removing the temporary process layer prior to forming the metal layer (Fan, paragraph 0044 teaches the removal of the temporary process layer 602 prior to the formation of the metal layer 802, which takes place in Fig. 8 and paragraph 0045).
Regarding Claim 14, Kim in view of Fan teaches the method according to claim 10, wherein the temporary process layer is an organic material layer (Fan, Fig. 6, temporary process layer 602. Paragraph 0043 teaches 602 is an organic layer).
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of Reference Cited (PTO-892) attached herewith.
Conclusion
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/V.R.G./Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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