DETAILED ACTION
This correspondence is in response to the communications received 02/18/2026. Claims 13-17 have been withdrawn. Claims 1-19 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-12, 18 in the reply filed on 02/18/2026 is acknowledged.
Claims 13-17 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected inventive group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/18/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/03/2023 and 04/09/2024 have been considered by the examiner and made of record in the application file.
Drawings
The drawings are objected to because several figures, chiefly the plots shown in Figs. 6-14, 17-23, 29-30, 33, and 37-40 as well as Figs 24-26 and 28, are of sufficiently low resolution as to be illegible. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 19 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention. The phrase “functional completeness” is defined in ¶[74] of the specification as “when the in-memory computing device is used in a set, a group similar to a set, or a member containing such a set or group as a property, it can be used to express all possible truth tables by combining the configuration with Boolean expressions”. However, this definition fails to sufficiently described the claimed subject matter as to reasonable convey that the inventors, at the time the application was filed, had possession of the claimed invention. It is unclear how to fully achieve the claimed functionality merely from the structure and the “in-memory-computing device”, thus claim 19 fails to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 3, 4, 7-9, 11, 18 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 requires “a material having non-dielectric and insulating characteristics”. The phrase “non-dielectric” is unclear. One having ordinary skill in the art would recognize that any insulating material will show some amount of dielectric behavior, even if it is negligible. Thus, it is unclear what the threshold for “non-dielectric” materials is. Claims 3 and 4 are rejected for their dependence on claim 2.
Claim 4 requires “wherein the insulating layer contains h-BN”. However, claim 2 requires the insulating layer to be “a material having non-dielectric and insulating characteristics”. According to Table 1 of Laturia et al. (Dielectric properties of hexagonal boron nitride and transition metal dichalcogenides: from monolayer to bulk, npj 2D materials and applications) the dielectric constant of h-BN is around 3-7 depending on layer orientation and measurement frequency. One having ordinary skill in the art would know that silicon oxide, a well-known dielectric material, has a dielectric constant around 3.5. Thus, it is unclear how h-BN could constitute a “non-dielectric”.
Claim 7 requires “wherein when a voltage equal to or higher than a predetermined first threshold voltage is applied between the source electrode and the drain electrode, the first polarization layer is polarized in a horizontal direction, or a polarization state is released, and when a voltage is applied to the gate electrode, the second polarization layer is polarized in a vertical direction, or the polarization state is released, and whether the first polarization layer is polarized and whether the second polarization layer is polarized independently determine electrical conductivity of the first polarization layer.” This limitation is interpretated as functional language that merely recites the function achieved by the claimed invention without providing a clear-cut indication of the scope of the subject matter embraced by the claim and is thus indefinite. See MPEP 2173.05(g). Claims 8 and 9 are rejected for their dependence on claim 7.
MPEP 2173.05(g) states: Notwithstanding the permissible instances, the use of functional language in a claim may fail "to provide a clear-cut indication of the scope of the subject matter embraced by the claim" and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255, 85 USPQ2d 1654, 1663 (Fed. Cir. 2008) (noting that the Supreme Court explained that a vice of functional claiming occurs "when the inventor is painstaking when he recites what has already been seen, and then uses conveniently functional language at the exact point of novelty") (quoting General Elec. Co. v. Wabash Appliance Corp., 304 U.S. 364, 371 (1938)).
Claim 8 requires “wherein when the first polarization layer and the second polarization layer are polarized in the horizontal and vertical directions, respectively, the polarization layers are polarized to be saturated.” This limitation is interpretated as functional language that merely recites the function achieved by the claimed invention without providing a clear-cut indication of the scope of the subject matter embraced by the claim and is thus indefinite. See MPEP 2173.05(g).
Claim 9 requires “wherein the junction structure element may have
a first resistance state;
a fourth resistance state having an electrical conductivity higher than that of the first resistance state;
a second resistance state having an electrical conductivity between the first resistance state and the fourth resistance state; and
a third resistance state having an electrical conductivity between the second resistance state and the fourth resistance state,
wherein the first resistance state is implemented by applying a positive voltage between the source electrode and the drain electrode and a negative voltage to the gate electrode,
the second resistance state is implemented by applying a negative voltage between the source electrode and the drain electrode and a negative voltage to the gate electrode,
the third resistance state is implemented by applying a positive voltage between the source electrode and the drain electrode and a positive voltage to the gate electrode, and
the fourth resistance state is implemented by applying a negative voltage between the source electrode and the drain electrode and a positive voltage to the gate electrode.” This limitation is interpretated as functional language that merely recites the function achieved by the claimed invention without providing a clear-cut indication of the scope of the subject matter embraced by the claim and is thus indefinite. See MPEP 2173.05(g).
Claim 11 requires “the gate electrode contains Si/SiO2”. This limitation is indefinite as it is unclear the meaning incurred by the use of the forward slash. For the purposes of examination “the gate electrode contains Si/SiO2” will be interpretated as “the gate electrode contains Si and SiO2”.
Claim 18 requires “wherein the junction structure element may have
a first resistance state;
a fourth resistance state having an electrical conductivity higher than that of the first resistance state;
a second resistance state having an electrical conductivity between the first resistance state and the fourth resistance state; and
a third resistance state having an electrical conductivity between the second resistance state and the fourth resistance state, and direct transition between the first to fourth resistance states is possible.” This limitation is interpretated as functional language that merely recites the function achieved by the claimed invention without providing a clear-cut indication of the scope of the subject matter embraced by the claim and is thus indefinite. See MPEP 2173.05(g). Claim 19 is rejected for its dependence on claim 18.
Claim 19 requires “having functional completeness.” This limitation is interpretated as functional language that merely recites the function achieved by the claimed invention without providing a clear-cut indication of the scope of the subject matter embraced by the claim and is thus indefinite. See MPEP 2173.05(g). While the phrase “functional completeness” is defined in ¶[74] of the specification, in is unclear how this definition is implemented by the in-memory-computing device.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
PNG
media_image1.png
276
606
media_image1.png
Greyscale
Regarding claim 1, a junction structure element (100) comprising:
a first polarization layer (101) containing a material having a ferroelectric characteristic of being polarized only horizontally (see [50]);
a second polarization layer (102) disposed on the first polarization layer (see Fig. 1) and containing a material having a ferroelectric characteristic of being polarized only vertically (see [51]);
a source electrode (104) and a drain electrode (105) each in contact with the first polarization layer and spaced apart from each other (see Fig. 1); and
a gate electrode (106) disposed on the second polarization layer (see Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Singh et al. (Two-Dimensional CIPS-InSe van Der Waal Heterostructure Ferroelectic Field Effect Transistor for Nonvolatile Memory Applications, published 03/02/2022, ACS Nano) in view of Bao et al. (Gate-Tunable In-Plane Ferroelectricity in Few-Layer SnS, published 06/28/2019, Nano Letters) in view of Kim et al. (Ferroelectric field effect transistors: Progress and perspective, published 02/02/2021, APL Materials) in view of Ming et al. (Flexoelectric engineering of van der Waals ferroelectric CuInP2S6, published 08/19/2022, Science Advances).
PNG
media_image2.png
326
564
media_image2.png
Greyscale
Regarding claim 1, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh disclose a junction structure element (see title) comprising:
a first polarization layer (as seen in in Fig. 1(a) the “InSe” layer is a first layer, where “Recent 2D vdW ferroelectrics such as Group III−VI compounds, (InSe and Tl2O) Group IV−VI compounds, (GeS, GeSe, SnTe, SnSe, and SnS), CuInP2S6 (CIPS), α-In2Se3, BA2PbCl4, and so on display stable polarization above room temperature and at a thickness down to a few atomic layers”, pg. 5419, left column, line 23, right column lines 1-5, thus InSe is a first polarization layer) containing a material having a ferroelectric characteristic of being polarized only horizontally (Singh does not disclose InSe having a ferroelectric characteristic of being polarized only horizontally, however a secondary reference will be used to teach this limitation below);
a second polarization layer (as seen in Fig. 1(a) and referenced above, the “CIPS” layer is a second polarization layer) disposed on the first polarization layer (as seen in Fig. 1(a), the CIPS layer is on the InSe layer) and containing a material having a ferroelectric characteristic of being polarized only vertically (Singh does not disclose CIPS having a ferroelectric characteristic of being polarized only vertically, however a secondary reference will be used to teach this limitation below);
a source electrode and a drain electrode each in contact with the first polarization layer and spaced apart from each other (as seen in Fig. 1(a), there are source and drain electrodes labeled “Source” and “Drain” respectively, that are each in contact with the InSe layer and spaced apart from each other); and
a gate electrode disposed on the second polarization layer (as seen in Fig. 1(a) there is a gate electrode labeled “Gate”, that is disposed on the CIPS layer).
Singh fails to disclose “a first polarization layer containing a material having a ferroelectric characteristic of being polarized only horizontally;
a second polarization layer disposed on the first polarization layer and containing a material having a ferroelectric characteristic of being polarized only vertically”.
However, in a similar field of endeavor, Bao teaches a first polarization layer containing a material having a ferroelectric characteristic of being polarized only horizontally (“we have observed robust in-plane ferroelectricity in ultrathin films of 2D SnS”, pg. 5115, left column, lines 29-30, where “in-plane” is interpretated as being in the plane of the film, which is horizontal, the InSe film of Singh is substituted for the SnS film of Bao. As discussed previously, Singh discloses that InSe and SnS display similar ferroelectric properties, and further, as seen in Table I of Kim, SnS has a greater polarization and dielectric constant relative to InSe).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement a first polarization layer containing a material having a ferroelectric characteristic of being polarized only horizontally as taught by Bao and Kim in the system of Singh for the purpose of tuning the electrical properties of the first polarization layer.
Singh in combination with Bao and Kim fail to disclose “a second polarization layer disposed on the first polarization layer and containing a material having a ferroelectric characteristic of being polarized only vertically”.
However, in a similar field of endeavor, Ming teaches a second polarization layer disposed on the first polarization layer and containing a material having a ferroelectric characteristic of being polarized only vertically (“Van der Waals layered CuInP2S6 (CIPS) has generated great excitement in recent years because of its room temperature ferroelectricity with out-of-plane spontaneous polarization”, pg. 1, left column, lines 1-3, , where “in-plane” is interpretated as being out of the plane of the film, which is vertical).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a second polarization layer disposed on the first polarization layer and containing a material having a ferroelectric characteristic of being polarized only vertically” as taught by Ming in the system of Singh in combination with Bao and Kim for the purpose of identifying the direction of polarization of the CIPS film of Singh.
Regarding claim 2, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 1, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh further disclose further comprising an insulating layer (as seen in in Fig. 1(a) the “h-BN” layer is an insulating layer, where “Through the mechanical exfoliation technique, a ferroelectric CIPS layer has been integrated with the InSe channel with a few layers of hexagonal-boron nitride (h-BN) as an insulator”, pg. 5419, right column, lines 11-14, thus the h-BN layer is an insulating layer) disposed between the first polarization layer and the second polarization layer (as seen in Fig. 1(a) the h-BN layer is between the InSe and CIPS layers) and containing a material having non-dielectric and insulating characteristics (¶[58] of the instant specification states “the insulating layer 103 may contain h-BN”, thus as Singh teaches the same composition of the insulating layer, the claimed insulation layer and the insulation layer taught by Singh must have the same properties, see MPEP 2112.01 II).
MPEP 2112.01 II states “Products of identical chemical composition can not have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present.
Regarding claim 3, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 2, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh further disclose wherein thickness of the insulating layer is 5 to 15nm (“h-BN (∼8 nm) as the insulating layer”, pg. 5421, left column, lines 18-19).
Regarding claim 4, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 2, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh further disclose wherein the insulating layer contains h-BN (as discussed above the insulation layer contains h-BN).
Regarding claim 5, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 1, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh and Bao further disclose wherein the first polarization layer and the second polarization layer contain one or more materials independently and differently selected from a group including CuInP2S6 (CIPS) and SnS (as discussed above, Ming discloses that the first polarization layer can contain SnS, and Singh discloses that the second polarization layer contains CIPS).
Regarding claim 6, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 5, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh and Bao further disclose wherein the first polarization layer contains SnS, and the second polarization layer contains CIPS (as discussed above, Ming discloses that the first polarization layer can contain SnS, and Singh discloses that the second polarization layer contains CIPS).
Regarding claim 7, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 1, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh further disclose wherein when a voltage equal to or higher than a predetermined first threshold voltage is applied between the source electrode and the drain electrode, the first polarization layer is polarized in a horizontal direction, or a polarization state is released, and when a voltage is applied to the gate electrode, the second polarization layer is polarized in a vertical direction, or the polarization state is released, and whether the first polarization layer is polarized and whether the second polarization layer is polarized independently determine electrical conductivity of the first polarization layer (Singh in combination with Bao, Kim, and Ming disclose a substantially identical structure to the claimed structure, therefor as per MPEP 2112.01 I, the structure disclosed by Singh in combination with Bao, Kim, and Ming would inherently share the same properties and functionality as the claimed structure).
MPEP 2112.01 I states where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). "When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
PNG
media_image3.png
1157
1298
media_image3.png
Greyscale
Regarding claim 8, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 7, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh further disclose wherein when the first polarization layer and the second polarization layer are polarized in the horizontal and vertical directions, respectively (as discussed previously, the InSe layer of Singh can be replaced with a horizontally polarized SnS layer disclosed by Bao, and the CIPS layer is vertically polarized), the polarization layers are polarized to be saturated (“In a conventional FeFET structure, only polarization bound charges exist. These switch under the presence of an external electric field and modulate the channel conductance”, pg. 5423, right column, lines 6-9, thus channel conductance depends on polarization bound charges, and as seen in Fig. 3(b) the channel conductance plateaus, thus indicating the polarization bound charges are saturated).
Regarding claim 9, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 7, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh further disclose wherein the junction structure element may have
a first resistance state;
a fourth resistance state having an electrical conductivity higher than that of the first resistance state;
a second resistance state having an electrical conductivity between the first resistance state and the fourth resistance state; and
a third resistance state having an electrical conductivity between the second resistance state and the fourth resistance state,
wherein the first resistance state is implemented by applying a positive voltage between the source electrode and the drain electrode and a negative voltage to the gate electrode,
the second resistance state is implemented by applying a negative voltage between the source electrode and the drain electrode and a negative voltage to the gate electrode,
the third resistance state is implemented by applying a positive voltage between the source electrode and the drain electrode and a positive voltage to the gate electrode, and
the fourth resistance state is implemented by applying a negative voltage between the source electrode and the drain electrode and a positive voltage to the gate electrode (Singh in combination with Bao, Kim, and Ming disclose a substantially identical structure to the claimed structure, therefor as per MPEP 2112.01 I, the structure disclosed by Singh in combination with Bao, Kim, and Ming would inherently share the same properties and functionality as the claimed structure).
MPEP 2112.01 I states where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). "When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Regarding claim 10, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 1, Bao further discloses wherein thickness of the first polarization layer is 5 to 15nm (“15 nm thick SnS films were chosen to fabricate devices to ensure a good channel conductivity”, pg. 5113, left column, lines 19-21).
Figs. 1(a)-1(h) and 3(a)-3(c) of Singh further disclose the thickness of the second polarization layer is 60 to 100nm (“CIPS (∼70 nm) as the top ferroelectric”, pg. 5421, left column, line 18).
Regarding claim 11, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 1, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh further disclose wherein each of the source electrode and the drain electrode contains one or more materials selected from a group including titanium (Ti) and gold (Au) (The source, drain, and gate patterns were defined by e-beam lithography. Furthermore, In and Au were deposited (10 and 60 nm, respectively) by e-beam evaporation to obtain the top gate, source, and drain contacts”, pg. 5421, left column, lines 21-24).
Figs. 1(a)-1(h) and 3(a)-3(c) of Singh fail to disclose “the gate electrode contains Si/SiO2”.
PNG
media_image4.png
1098
782
media_image4.png
Greyscale
However, in a similar field of endeavor, Figs. 2(a)-2(e) of Singh disclose the gate electrode contains Si/SiO2 (as seen in Fig. 2e, the gate electrode is SiO2 and Si).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “the gate electrode contains Si/SiO2” as taught by Figs. 2(a)-2(e) of Singh in the system of Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming for the purpose of simplifying the manufacturing process by utilizing the substrate as a gate electrode.
Regarding claim 12, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh disclose a junction structure element (see title) comprising:
a first polarization layer (as seen in in Fig. 1(a) the “InSe” layer is a first layer, where “Recent 2D vdW ferroelectrics such as Group III−VI compounds, (InSe and Tl2O) Group IV−VI compounds, (GeS, GeSe, SnTe, SnSe, and SnS), CuInP2S6 (CIPS), α-In2Se3, BA2PbCl4, and so on display stable polarization above room temperature and at a thickness down to a few atomic layers”, pg. 5419, left column, line 23, right column lines 1-5, thus InSe is a first polarization layer) containing a material having a ferroelectric characteristic of being polarized only horizontally (Singh does not disclose InSe having a ferroelectric characteristic of being polarized only horizontally, however a secondary reference will be used to teach this limitation below);
a second polarization layer (as seen in Fig. 1(a) and referenced above, the “CIPS” layer is a second polarization layer) disposed on the first polarization layer (as seen in Fig. 1(a), the CIPS layer is on the InSe layer) and containing a material having a ferroelectric characteristic of being polarized only vertically (Singh does not disclose CIPS having a ferroelectric characteristic of being polarized only vertically, however a secondary reference will be used to teach this limitation below);
a source electrode and a drain electrode each in contact with the first polarization layer and spaced apart from each other (as seen in Fig. 1(a), there are source and drain electrodes labeled “Source” and “Drain” respectively, that are each in contact with the InSe layer and spaced apart from each other); and
a gate electrode disposed on the second polarization layer (as seen in Fig. 1(a) there is a gate electrode labeled “Gate”, that is disposed on the CIPS layer).
Singh fails to disclose “a first polarization layer containing a material having a ferroelectric characteristic of being polarized only horizontally;
a second polarization layer disposed on the first polarization layer and containing a material having a ferroelectric characteristic of being polarized only vertically”.
However, in a similar field of endeavor, Bao teaches a first polarization layer containing a material having a ferroelectric characteristic of being polarized only horizontally (“we have observed robust in-plane ferroelectricity in ultrathin films of 2D SnS”, pg. 5115, left column, lines 29-30, where “in-plane” is interpretated as being in the plane of the film, which is horizontal, the InSe film of Singh is substituted for the SnS film of Bao. As discussed previously, Singh discloses that InSe and SnS display similar ferroelectric properties, and further, as seen in Table I of Kim, SnS has a greater polarization and dielectric constant relative to InSe).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement a first polarization layer containing a material having a ferroelectric characteristic of being polarized only horizontally as taught by Bao and Kim in the system of Singh for the purpose of tuning the electrical properties of the first polarization layer.
Singh in combination with Bao and Kim fail to disclose “a second polarization layer disposed on the first polarization layer and containing a material having a ferroelectric characteristic of being polarized only vertically”.
However, in a similar field of endeavor, Ming teaches a second polarization layer disposed on the first polarization layer and containing a material having a ferroelectric characteristic of being polarized only vertically (“Van der Waals layered CuInP2S6 (CIPS) has generated great excitement in recent years because of its room temperature ferroelectricity with out-of-plane spontaneous polarization”, pg. 1, left column, lines 1-3, , where “in-plane” is interpretated as being out of the plane of the film, which is vertical).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a second polarization layer disposed on the first polarization layer and containing a material having a ferroelectric characteristic of being polarized only vertically” as taught by Ming in the system of Singh in combination with Bao and Kim for the purpose of identifying the direction of polarization of the CIPS film of Singh.
PNG
media_image5.png
414
468
media_image5.png
Greyscale
Figs. 1(a)-1(h) and 3(a)-3(c) of Singh and Bao further disclose each of the first polarization layer and the second polarization layer may independently have polarization directions of two states including a direction from an anode to a cathode or a direction from the cathode to the anode, there may be a total of four states (as seen in Fig. 3(c) of Singh the polarization direction of the CIPS layer can alternate between two states based on the applied voltage, further, Fig. 4(a) of Bao shows “When the positive bias (+4.3 V) is larger than the coercive field, the negatively polarized SnS domains start to reverse to positive polarizations”, pg. 5113, right column, lines 19-21, thus both layers have two polarization states, resulting in a total of four states).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Singh et al. (Two-Dimensional CIPS-InSe van Der Waal Heterostructure Ferroelectic Field Effect Transistor for Nonvolatile Memory Applications, published 03/02/2022, ACS Nano) in view of Bao et al. (Gate-Tunable In-Plane Ferroelectricity in Few-Layer SnS, published 06/28/2019, Nano Letters) in view of Kim et al. (Ferroelectric field effect transistors: Progress and perspective published 02/02/2021, APL Materials) in view of Ming et al. (Flexoelectric engineering of van der Waals ferroelectric CuInP2S6, published 08/19/2022, Science Advances) in view of Gao et al. (US 20220277199 A1, published 09/01/2022).
Regarding claim 18, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, and Ming disclose the junction structure element according to claim 1, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh further disclose wherein the junction structure element may have
a first resistance state;
a fourth resistance state having an electrical conductivity higher than that of the first resistance state;
a second resistance state having an electrical conductivity between the first resistance state and the fourth resistance state; and
a third resistance state having an electrical conductivity between the second resistance state and the fourth resistance state, and direct transition between the first to fourth resistance states is possible (Singh in combination with Bao, Kim, and Ming disclose a substantially identical structure to the claimed structure, therefor as per MPEP 2112.01 I, the structure disclosed by Singh in combination with Bao, Kim, and Ming would inherently share the same properties and functionality as the claimed structure).
MPEP 2112.01 I states where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). "When the PTO shows a sound basis for believing that the products of the applicant and the prior art are the same, the applicant has the burden of showing that they are not." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990).
Singh in combination with Bao, Kim, and Ming fails to disclose “an in-memory-computing device comprising a junction structure element”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Gao teaches an in-memory-computing device comprising a junction structure element (“Each of the plurality of neural network matrices may include a plurality of in-memory computing units”, [0084], where “The in-memory computing unit is not specifically limited in this embodiment of this application, and may include but is not limited to a memristor, a static RAM (SRAM), a NOR flash, a magnetic RAM (MRAM), a ferroelectric gate field-effect transistor (FeFET), and an electrochemical RAM (ECRAM)”, [0085], thus the FeFET disclosed by Singh can be implemented in the in-memory computing unit of Gao).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “an in-memory-computing device comprising a junction structure element” as taught by Gao in the system of Singh in combination with Bao, Kim, and Ming for the purpose of providing a device to enable the functionality of the structure disclosed by Singh.
Regarding claim 19, Figs. 1(a)-1(h) and 3(a)-3(c) of Singh in combination with Bao, Kim, Ming, and Gao disclose the junction structure element according to claim 18, Gao further discloses having functional completeness (Singh in combination with Bao, Kim, Ming, and Gao disclose a substantially identical structure to the claimed structure, therefor as per MPEP 2112.01 I, the structure disclosed by Singh in combination with Bao, Kim, and Ming would inherently share the same properties and functionality as the claimed structure).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights