DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species D, Claims 1-18 in the reply filed on 02/24/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/03/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the "the third power terminal ...is electrically connected to both the first switching element and the second switching element via the second conductive part" must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 10-14, and 18 are rejected under U.S.C. 103 as being unpatentable over Saitou; US 2007/0161285 A1; 11/2004 in view of Hatano; US 11,721,612 B2; 09/2019
Claim 1: Saitou discloses a semiconductor device comprising: a terminal ( Fig. 8: external connecting terminals 108 ) including an electrically conductive tubular holder ( Fig. 8: holder hole 103 ) and a metal pin inserted into the holder ( Fig. 8: electrically conductive contacts 104 ); a signal substrate ( Fig. 8: circuit board 106 ) including a wiring layer ( Fig. 8: electrode 105 ) and an insulating substrate ( the base material of a printed circuit board is inherently an insulating substrate ); and the holder ( Fig. 8 #103 ) is bonded to the wiring layer ( Fig. 8 #105 ), the metal pin ( Fig. 8 #104 ) extends in the thickness direction ( as shown in Fig. 8 ).
Saitou does not appear to disclose a supporting conductor supporting the wiring layer via the insulating substrate; and a bonding layer interposed between the supporting conductor and the signal substrate, wherein the insulating substrate includes an obverse surface and a reverse surface that are spaced apart in a thickness direction of the signal substrate, the wiring layer is disposed on the obverse surface, and the terminal is secured to the wiring layer, and the bonding layer includes an insulating layer that electrically insulates the signal substrate and the supporting conductor.
However, Hatano teaches a supporting conductor ( Fig. 3 conductive substrate 22A ) supporting the wiring layer ( Fig. 3 plurality of wires 6 ) via the insulating substrate ( Fig. 3 substrate 21 ) ; and a bonding layer ( Fig. 3 conductive bonding layer 3 ) interposed between the supporting conductor ( Fig. 3 #22A and #22B ) and the signal substrate ( Fig. 3: support substrate 20 ), wherein the insulating substrate ( Fig. 3 #21 ) includes an obverse surface and a reverse surface ( as shown in Fig. 3 ) that are spaced apart in a thickness direction of the signal substrate ( Fig. 3 #20 ), the wiring layer ( Fig. 3 #6 ) is disposed on the obverse surface ( Col. 6 lines 1-4 The obverse face electrode 11 is provided on the element obverse face 101. The obverse face electrode 11 includes a first electrode 111 and a second electrode 112, as shown in FIG. 4 and FIG. 11 ), and the terminal ( Fig. 3 terminals 44A, 44B, 45A, and 45B ) is secured to the wiring layer ( Col. 16 lines 8-11 the plurality of wires 6 include a plurality of gate wires 61, a plurality of detection wires 62, a pair of first connection wires 63, and a pair of second connection wires 64; Col. 16 lines 12-15 The plurality of gate wires 61each have one end bonded to the second electrode 112 (gate electrode) of the semiconductor element 10, and the other end bonded to one of the pair of gate layers 24A and 24B ), and the bonding layer ( Fig. 3 #3 ) includes an insulating layer ( Fig. 4: insulating film 13 ) that electrically insulates the signal substrate ( Fig. 3 #20 ) and the supporting conductor ( Fig. 3 #22A and #22B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou to implement a supporting conductor supporting the wiring layer via the insulating substrate; and a bonding layer interposed between the supporting conductor and the signal substrate, wherein the insulating substrate includes an obverse surface and a reverse surface that are spaced apart in a thickness direction of the signal substrate, the wiring layer is disposed on the obverse surface, and the terminal is secured to the wiring layer, and the bonding layer includes an insulating layer that electrically insulates the signal substrate and the supporting conductor because this approach will improve the mechanical reliability, thermal management, and electrical performance of a semiconductor package.
Claim 2: Saitou and Hatano disclose the semiconductor device according to claim 1 ( as discussed above).
Saitou does not appear to disclose the bonding layer further includes a pair of adhesive layers disposed on opposite sides of the insulating layer in the thickness direction.
However, Hatano teaches the bonding layer ( Fig. 3 #3 ) further includes a pair of adhesive layers ( Fig. 3 #31A and #31B ) disposed on opposite sides of the insulating layer ( Fig. 3 #13 ) in the thickness direction ( as shown in Fig. 3 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou to implement the bonding layer further includes a pair of adhesive layers disposed on opposite sides of the insulating layer in the thickness direction because this approach will bridge different materials, manage thermal stress, and enhance bonding reliability.
Claim 6: Saitou and Hatano disclose the semiconductor device according to claim 2 ( as discussed above).
Saitou does not appear to disclose the insulating layer is a film-like layer.
However, Hatano teaches the insulating layer is a film-like layer ( Col. 6 lines 23 – 26 The insulation film 13 is, for example, composed of a silicon dioxide (SiO.sub.2) layer, a silicon nitride (SiN.sub.4) layer, and a polybenzoxazole layer, stacked in this order from the element obverse face 101 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou to implement the insulating layer is a film-like layer because this approach is used to achieve precise electrical control, enable extreme miniaturization, and reduce power consumption.
Claim 10: Saitou and Hatano disclose the semiconductor device according to claim 1 ( as discussed above).
Saitou does not appear to disclose the signal substrate includes a metal layer disposed on the reverse surface, and the metal layer is bonded to the supporting conductor by the bonding layer.
However, Hatano teaches the signal substrate ( Fig. 11: semiconductor elements 10A ) includes a metal layer disposed on the reverse surface ( Fig. 11 reverse face electrode 12 ), and the metal layer is bonded to the supporting conductor ( Fig. 11: conductive substrate 22A ) by the bonding layer ( Fig. 11: element bonding layer 31A ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou to implement the signal substrate includes a metal layer disposed on the reverse surface, and the metal layer is bonded to the supporting conductor by the bonding layer because this approach would improve electrical, thermal, and mechanical performance.
Claim 11: Saitou and Hatano disclose the semiconductor device according to claim 10 ( as discussed above).
Saitou does not appear to disclose a semiconductor element electrically connected to the terminal, wherein the semiconductor element is bonded to the supporting conductor.
However, Hatano teaches a semiconductor element ( Fig. 4: gate layers 24A and 24B, and detection layers 25A and 25B ) electrically connected to the terminal ( Fig. 4: 24A is connected to 44A, 24B is connected to 44B, 25A is connected to 45A, and 25B is connected to 45B ), wherein the semiconductor element ( Fig. 4, 24A, 24B, 25A, and 25B ) is bonded to the supporting conductor ( as shown in Fig. 9 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou to implement a semiconductor element electrically connected to the terminal, wherein the semiconductor element is bonded to the supporting conductor because this approach achieves mechanical stability, thermal management, and electrical performance.
Claim 12: Saitou and Hatano disclose the semiconductor device according to claim 11 ( as discussed above).
Saitou does not appear to disclose the terminal is a control terminal for controlling the semiconductor element.
However, Hatano teaches the terminal ( Fig. 3: gate terminals 44A and 44B ) is a control terminal for controlling the semiconductor element ( Col. 16 lines 30-36 Of the pair of first connection wires 63, as shown in FIG. 3 and FIG. 4, one connects the gate layer 24A and the gate terminal 44A, and the other connects the gate layer 24B and the gate terminal 44B. The one of the first connection wires 63 has one end bonded to the gate layer 24A, and the other end bonded to the pad portion 441of the gate terminal 44A, thus electrically connecting therebetween ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou to implement the terminal is a control terminal for controlling the semiconductor element because this allows a small input signal- voltage or current – to modulate the conductivity of the material between the main power terminals.
Claim 13: Saitou and Hatano disclose the semiconductor device according to claim 12 ( as discussed above).
Saitou does not appear to disclose the supporting conductor includes a first conductive part and a second conductive part that are spaced apart from each other in a first direction orthogonal to the thickness direction, the semiconductor element includes a first switching element bonded to the first conductive part and a second switching element bonded to the second conductive part, the control terminal includes a first control terminal for controlling the first switching element and a second control terminal for controlling the second switching element, the signal substrate includes a first signal substrate supporting the first control terminal and a second signal substrate supporting the second control terminal, and the bonding layer includes a first bonding body bonding the first signal substrate to the first conductive part and a second bonding body bonding the second signal substrate to the second conductive part.
However, Hatano teaches the supporting conductor ( Fig. 3 #22 ) includes a first conductive part ( Fig. 3 #22A ) and a second conductive part ( Fig. 3 #22B ) that are spaced apart from each other in a first direction orthogonal to the thickness direction ( as shown in Fig. 4 ), the semiconductor element includes a first switching element ( Fig. 4 #10A ) bonded to the first conductive part ( Fig. 4 #22A ) and a second switching element ( Fig. 4 #10B ) bonded to the second conductive part ( Fig. 4 #22B ), the control terminal includes a first control terminal ( Fig. 4 #44A ) for controlling the first switching element ( Fig. 4 #24A ) and a second control terminal ( Fig. 4 #44B ) for controlling the second switching element ( Fig. 4 #24B ), the signal substrate ( Fig. 3 #20 ) includes a first signal substrate supporting the first control terminal ( Col. 24 lines 28 – 32 the support substrate 20 may include two insulation substrates 21A and 21B, so that the insulation substrate 21A may support the conductive substrate 22A, and the insulation substrate 21B may support the conductive substrate 22B ) and a second signal substrate ( as discussed above ) supporting the second control terminal ( as discussed above ), and the bonding layer ( Fig. 4 #3 ) includes a first bonding body ( Fig. 4 #31A ) bonding the first signal substrate ( Col. 10 lines 28 – 30 The plurality of element bonding layers 31A each serve to bond the semiconductor elements 10A to the conductive substrate 22A ) to the first conductive part ( Fig. 4 #22A ) and a second bonding body ( Fig. 4 #31B ) bonding the second signal substrate to the second conductive part ( Col. 10 lines 44-46 The plurality of element bonding layers 31B each serve to bond the semiconductor elements 10B to the conductive substrate 22B ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou to implement the supporting conductor includes a first conductive part and a second conductive part that are spaced apart from each other in a first direction orthogonal to the thickness direction, the semiconductor element includes a first switching element bonded to the first conductive part and a second switching element bonded to the second conductive part, the control terminal includes a first control terminal for controlling the first switching element and a second control terminal for controlling the second switching element, the signal substrate includes a first signal substrate supporting the first control terminal and a second signal substrate supporting the second control terminal, and the bonding layer includes a first bonding body bonding the first signal substrate to the first conductive part and a second bonding body bonding the second signal substrate to the second conductive part because the architectural configuration is designed to optimize power density, thermal management, and electrical performance in high-power semiconductor modules.
Claim 14: Saitou and Hatano disclose the semiconductor device according to claim 13 ( as discussed above).
Saitou does not appear to disclose the first control terminal includes a first drive terminal for driving the first switching element and a first sensing terminal for sensing a conducting state of the first switching element, and the second control terminal includes a second drive terminal for driving the second switching element and a second sensing terminal for sensing a conducting state of the second switching element.
However, Hatano teaches the first control terminal ( Fig. 4 #44A ) includes a first drive terminal ( Col. 28 lines 15 – 17 The obverse face metal layer 27A is electrically connected to the respective reverse face electrodes 12 (drain electrodes) of the semiconductor elements 10A ) for driving the first switching element ( Fig. 4 #10A ) and a first sensing terminal ( Fig. 4: detection terminal 45A ) for sensing a conducting state of the first switching element ( Col. 9 lines 51 – 55 The detection layer 25A is electrically connected to the second electrode 111 (source electrode) of each semiconductor element 10A, via a wire 6 ), and the second control terminal ( Fig. 4 #44B ) includes a second drive terminal ( Col. 28 lines 32 – 35 The obverse face metal layer 27B is electrically connected to the respective reverse face electrodes 12 (drain electrodes) of the semiconductor elements 10B) for driving the second switching element ( Fig. 4 #10B ) and a second sensing terminal ( Fig. 4: detection terminal 45B ) for sensing a conducting state of the second switching element ( Col. 9 line 66 – Col. 10 line 3 The detection layer 25B is electrically connected to the second electrode 111 (source electrode) of each semiconductor element 10B, via a wire 6 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou to implement the first control terminal includes a first drive terminal for driving the first switching element and a first sensing terminal for sensing a conducting state of the first switching element, and the second control terminal includes a second drive terminal for driving the second switching element and a second sensing terminal for sensing a conducting state of the second switching element because this approach improves switching performance, enhances reliability, and provides precise, high-speed monitoring of the device’s operating state.
Claim 18: Saitou and Hatano disclose the semiconductor device according to claim 13 ( as discussed above).
Saitou does not appear to disclose a supporting substrate supporting the first conductive part and the second conductive part.
However, Hatano teaches a supporting substrate ( Fig. 3 support substrate 20 ) supporting the first conductive part ( Fig. 3 #22A ) and the second conductive part ( Fig. 3 #22B ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou to implement a supporting substrate supporting the first conductive part and the second conductive part because this approach provides structural integrity, manages thermal loads, and facilitates electrical interconnection between components.
Claim 3 is rejected under U.S.C. 103 as being unpatentable over Saitou; US 2007/0161285 A1; 11/2004 in view of Hatano; US 11,721,612 B2; 09/2019 as it relates to claim 1 above and further in view of Hidaka et al.; US 2023/0043148 A1; 12/2020
Claim 3: Saitou and Hatano disclose the semiconductor device according to claim 2 ( as discussed above ).
Neither Saitou nor Hatano appear to disclose a length of each of the pair of adhesive layers in the thickness direction is at least 10% and at most 150% of a length of the insulating layer in the thickness direction.
However, Hidaka teaches a length of each of the pair of adhesive layers in the thickness direction ( [0113] The thickness of the adhesive layer 104 can be freely selected and is preferably 100 µm or more and 200 µm or less and more preferably 130 µm or more and 170 µm or less ) is at least 10% and at most 150% of a length of the insulating layer in the thickness direction ( [0039] The thickness of the conductive layer 4 is freely selected, is, for example, preferably 5 to 200 µm, more preferably 8 to 150 µm, and still more preferably 10 to 100 µm, and is not limited to only these examples; [0048] it is preferable that the thickness of the insulating layer 5 is the same as the thickness of the conductive layer 4 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hidaka with Saitou and Hatano to implement a length of each of the pair of adhesive layers in the thickness direction is at least 10% and at most 150% of a length of the insulating layer in the thickness direction because this approach is a design strategy used to optimize mechanical durability, prevent delamination, and manage internal stresses.
Claim 4 is rejected under U.S.C. 103 as being unpatentable over Saitou; US 2007/0161285 A1; 11/2004 in view of Hatano; US 11,721,612 B2; 09/2019 as it relates to claim 1 above and further in view of Kanda et al.; US 2020/0266134 A1; 11/2018
Claim 4: Saitou and Hatano disclose the semiconductor device according to claim 1 ( as discussed above).
Neither Saitou nor Hatano appear to disclose a length of the insulating layer in the thickness direction is at least 0.1% and at most 1.0% of a length of the terminal in the thickness direction.
However, Kanda teaches a length of the insulating layer in the thickness direction ( [0064] The insulating layer 10 has a thickness t0 (size in the thickness direction z) of 0.25 to 0.5 mm if the constituent material thereof is a ceramic, and of 100 to 200 μm if the constituent material thereof is a heat dissipation sheet ) is at least 0.1% and at most 1.0% of a length of the terminal in the thickness direction ( [0081] The first supply terminal 31 has a thickness set to 0.5 to 1.5 mm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kanda with Saitou and Hatano to implement a length of the insulating layer in the thickness direction is at least 0.1% and at most 1.0% of a length of the terminal in the thickness direction because this approach is designed to balance electrical insulation with manufacturing constraints and reliability.
Claim 5 is rejected under U.S.C. 103 as being unpatentable over Saitou; US 2007/0161285 A1; 11/2004 in view of Hatano; US 11,721,612 B2; 09/2019 as it relates to claim 1 above and further in view of Terasaki; US 2022/0359340 A1; 10/2020
Claim 5: Saitou and Hatano disclose the semiconductor device according to claim 1 ( as discussed above ).
Neither Saitou nor Hatano appear to disclose a length of the terminal in the thickness direction is at least 20 times and at most 30 times a length of the signal substrate in the thickness direction.
However, Terasaki teaches a length of the terminal in the thickness direction ( [0130] A copper terminal (in a case of AlN: 10 mm×5 mm×1 mm in thickness, and in a case of Si.sub.3N.sub.4: 10 mm×10 mm×1 mm in thickness ) was ultrasonically bonded to the obtained insulating circuit substrate (copper/ceramic bonded body) using an ultrasonic metal bonding machine (60C-904 manufactured by Ultrasonic Engineering Co., Ltd.) ) is at least 20 times and at most 30 times a length ( 0.2 * 20 = 4 which is less than the first two thickness dimensions of the terminal ) of the signal substrate in the thickness direction ( [0047] The thickness of the ceramic substrate 11is set to be in a range of, for example, 0.2 mm or more and 1.5 mm or less, and in the present embodiment, the thickness is set to 0.635 mm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Terasaki with Saitou and Hatano to implement a length of the terminal in the thickness direction is at least 20 times and at most 30 times a length of the signal substrate in the thickness direction because this approach balances high-density electrical routing with mechanical reliability.
Claims 7 and 8 are rejected under U.S.C. 103 as being unpatentable over Saitou; US 2007/0161285 A1; 11/2004 in view of Hatano; US 11,721,612 B2; 09/2019 as it relates to claim 6 above and further in view of Nishimura et al.; US 2022/0352105 A1; 09/2020
Claim 7: Saitou and Hatano disclose the semiconductor device according to claim 6 ( as discussed above ).
Neither Saitou nor Hatano appear to disclose the insulating layer contains a resin material.
However, Nishimura teaches the insulating layer contains a resin material ( [0275] The insulation layer is, for example, an oxide film such as SiO.sub.2 or a resin film such as polyimide ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nishimura with Saitou and Hatano to implement the insulating layer contains a resin material because this approach provides superior electrical insulation, mechanical protection, moisture resistance, and thermal stability.
Claim 8: Saitou and Hatano disclose the semiconductor device according to claim 7 ( as discussed above ).
Neither Saitou nor Hatano appear to disclose the resin material is polyimide
However, Nishimura teaches the resin material is polyimide ( [0275] The insulation layer is, for example, an oxide film such as SiO.sub.2 or a resin film such as polyimide ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Nishimura with Saitou and Hatano to implement the resin material is polyimide because this approach provides thermal stability, superior electrical insulation, and mechanical flexibility.
Claim 9 is rejected under U.S.C. 103 as being unpatentable over Saitou; US 2007/0161285 A1; 11/2004 in view of Hatano; US 11,721,612 B2; 09/2019 as it relates to claim 1 above and further in view of Yano et al.; US 9357643 B2; 06/2014
Claim 9: Saitou and Hatano disclose the semiconductor device according to claim 1 ( as discussed above).
Saitou and Hatano do not appear to disclose the insulating substrate contains a ceramic material.
However, Yano teaches the insulating substrate contains a ceramic material ( Fig. 1: ceramic substrate 2 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Yano with Saitou and Hatano to implement the insulating substrate contains a ceramic material because this approach would manage intense heat, provide superior electrical insulation, and offer robust structural support.
Claims 15-17 are rejected under U.S.C. 103 as being unpatentable over Saitou; US 2007/0161285 A1; 11/2004 in view of Hatano; US 11,721,612 B2; 09/2019 as it relates to claim 13 and further in view of Kim et al.; US 11,838,020 B1; 02/2021
Claim 15: Saitou and Hatano disclose the semiconductor device according to claim 13 ( as discussed above).
Neither Saitou nor Hatano appear to disclose a first power terminal and a second power terminal to which a first power supply voltage is applied; and a third power terminal to which a second power supply voltage is applied, wherein the first power terminal is connected to the first conductive part and is electrically connected to the first switching element via the first conductive part, the second power terminal is electrically connected to the second switching element, and the third power terminal is connected to the second conductive part and is electrically connected to both the first switching element and the second switching element via the second conductive part.
However, Kim teaches a first power terminal ( Fig. 1A: VDD terminal ) and a second power terminal ( Fig. 1A: VDD_INT terminal ) to which a first power supply voltage is applied ( Col. 4 lines 53 – 56 The power gating circuit 15 may be coupled between a supply terminal of the power source voltage VDD and a supply terminal of a high voltage VDD_INT ); and a third power terminal ( Fig. 1A: VSS terminal ) to which a second power supply voltage is applied ( Col. 4 lines 46 – 50 a ground voltage VSS is continuously supplied to the first and second logic circuits 11 and 13 ), wherein the first power terminal is connected to the first conductive part ( Col. 4 lines 53 – 56 The power gating circuit 15 may be coupled between a supply terminal of the power source voltage VDD and a supply terminal of a high voltage VDD_INT ) and is electrically connected to the first switching element ( Fig. 1A #15 ) via the first conductive part ( as shown in Fig. 1A ), the second power terminal ( Fig. 1A: VDD_INT terminal ) is electrically connected to the second switching element ( Fig. 1A #11 ), and the third power terminal ( Fig. 1A: VSS terminal ) is connected to the second conductive part ( Col. 4 lines 56 – 59 The first and second logic circuits 11 and 13 may be coupled between the supply terminal of the high voltage VDD_INT and a supply terminal of the ground voltage VSS ) and is electrically connected to both the first switching element and the second switching element via the second conductive part ( Fig. 1A: VSS is connected to #11 and #13 not #15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim with Saitou and Hatano to implement a first power terminal and a second power terminal to which a first power supply voltage is applied; and a third power terminal to which a second power supply voltage is applied, wherein the first power terminal is connected to the first conductive part and is electrically connected to the first switching element via the first conductive part, the second power terminal is electrically connected to the second switching element, and the third power terminal is connected to the second conductive part and is electrically connected to both the first switching element and the second switching element via the second conductive part because this approach reduces parasitic inductance and improves switching efficiency.
Claim 16: Saitou, Hatano, and Kim disclose the semiconductor device according to claim 15 ( as discussed above ).
Neither Saitou nor Kim appear to disclose a resin member covering a portion of the first control terminal, a portion of the second control terminal, the first signal substrate, the second signal substrate, the first switching element and the second switching element, wherein each of the first control terminal and the second control terminal protrudes from the resin member in the thickness direction.
However, Hatano teaches a resin member ( Fig. 3 #7 ) covering a portion of the first control terminal ( Fig. 3 #44A ), a portion of the second control terminal ( Fig. 3 #44B ), the first signal substrate ( Fig. 3 #22A ), the second signal substrate ( Fig. 3 #22B ), the first switching element ( Fig. 3 #10A ) and the second switching element ( Fig. 3 #10B ), wherein each of the first control terminal ( Fig. 3 #44A ) and the second control terminal ( Fig. 3 #44B ) protrudes from the resin member ( Fig. 3 #7 ) in the thickness direction ( as shown in Fig. 3 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kim with Saitou and Hatano to implement a resin member covering a portion of the first control terminal, a portion of the second control terminal, the first signal substrate, the second signal substrate, the first switching element and the second switching element, wherein each of the first control terminal and the second control terminal protrudes from the resin member in the thickness direction because this approach optimizes high-power handling, improves electrical performance and ensures reliability in a compact space.
Claim 17: Saitou, Hatano, and Kim disclose the semiconductor device according to claim 16 ( as discussed above).
Neither Saitou nor Kim appear to disclose the resin member includes: a resin obverse surface and a resin reverse surface spaced apart in the thickness direction; and a pair of resin side surfaces located between the resin obverse surface and the resin reverse surface in the thickness direction, the pair of resin side surfaces are spaced apart from each other in the first direction, the first power terminal and the second power terminal protrude from one of the pair of resin side surfaces in the first direction, and the third power terminal protrudes from the other of the pair of resin side surfaces in the first direction.
However, Hatano teaches the resin member ( Fig. 3 #7 ) includes: a resin obverse surface ( Col. 16 lines 59 – 62 The sealing resin 7 includes a resin obverse face 71 ) and a resin reverse surface ( Col. 16 lines 59 – 62 a resin reverse face 72 ) spaced apart in the thickness direction ( as shown in Fig. 5 ); and a pair of resin side surfaces ( Col. 17 lines 5 – 8 The plurality of resin side faces 731 to 734 are each connected to both of the resin obverse face 71 and the resin reverse face 72, and interposed therebetween in the thickness direction z ) located between the resin obverse surface ( Fig. 5 #71 ) and the resin reverse surface ( Fig. 5 #72 ) in the thickness direction ( as discussed above ), the pair of resin side surfaces ( Fig. 3 #731 to #734 ) are spaced apart from each other in the first direction ( as shown in Fig. 3 ), the first power terminal ( Fig. 3 input terminal 41) and the second power terminal ( Fig. 3 input terminal 42 ) protrude from one of the pair of resin side surfaces in the first direction ( Fig. 3 #731 ), and the third power terminal ( Fig. 3 #43 ) protrudes from the other of the pair of resin side surfaces in the first direction ( Fig. 3 #732 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hatano with Saitou and Kim to implement the resin member includes: a resin obverse surface and a resin reverse surface spaced apart in the thickness direction; and a pair of resin side surfaces located between the resin obverse surface and the resin reverse surface in the thickness direction, the pair of resin side surfaces are spaced apart from each other in the first direction, the first power terminal and the second power terminal protrude from one of the pair of resin side surfaces in the first direction, and the third power terminal protrudes from the other of the pair of resin side surfaces in the first direction because this approach is designed to encapsulate and protect internal components while managing the high current and voltage typical of power modules.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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