DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1-6, 13-15, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Kang et al., US 2021/0193775 A1.
Claim 1. Kang et al., disclose a display device (such as the one in fig. 8), comprising:
-a substrate (item 100) having thereon an active area (top portion of item 100), a pad area adjacent to the active area (this limitation would read through [0063] wherein is disclosed a plurality of pads may be provided in the pad area PADA), and a link area between the active area and the pad area (this limitation would also read through [0063] wherein is disclosed the data driver for supplying data signals may be located on a film electrically connected to pads in the pad area PADA by using a chip on film (“COF”) method);
-and data lines disposed to extend from the pad area to the active area, wherein the data lines are disposed to overlap in groups of at least three data lines in the link area, and wherein the at least three data lines are disposed on different layers, respectively (this limitation would also read through [0071] wherein is disclosed the first portion FL1 of each of the connection lines FL may be in parallel with the first data lines DL1, and part of the first portion FL1 may overlap the first data lines DL1, or the first portion FL1 may be adjacent to the first data lines DL1. The first portion FL1 of each of the connection lines FL may extend in parallel with the first data lines DL1 arranged as a plurality of columns. The second portion FL2 of each of the connection lines FL may be in parallel with the scan lines SL, and part of the second portion FL2 may overlap the scan lines SL, or the second portion FL2 may be adjacent to the scan lines SL. The second portion FL2 of each of the connection lines FL may extend in parallel with the scan lines SL arranged as a plurality of rows. The third portion FL3 of each of the connection lines FL may be in parallel with the second data lines DL2, and part of the third portion FL3 may overlap the second data lines DL2, or the third portion FL3 may be adjacent to the second data lines DL2. The third portion FL3 of each of the connection lines FL may extend in parallel with the second data lines DL2 arranged as a plurality of columns).
Claims 2, 13. Kang et al., disclose the display device according to claim 1, wherein a first data line of the at least three data lines disposed on a lower layer includes a light shielding metal layer (item 129) disposed on the substrate.
Claims 3-5, 14, 15. Kang et al., disclose the display device according to claim 2, wherein a second data line of the at least three data lines disposed on a middle layer includes a first source/drain metal layer disposed on a lower insulating layer covering the light shielding metal layer, and wherein the middle layer is above the lower layer. This limitation would also read through [0102] wherein is disclosed the semiconductor layer of each of the first through seventh transistors T1 though T7 may include a source area and a drain area at both sides of the channel area. The semiconductor layer may include a source area S1 and a drain area D1 of the first transistor T1, a source area S2 and a drain area D2 of the second transistor T2, a source area S3 and a drain area D3 of the third transistor T3, a source area S4 and a drain area D4 of the fourth transistor T4, a source area S5 and a drain area D5 of the fifth transistor T5, a source area S6 and a drain area D6 of the sixth transistor T6, and a source area S7 and a drain area D7 of the seventh transistor T7. The source area or drain area may correspond to a source electrode or drain electrode of the transistor. In another exemplary embodiment, locations of the source area and the drain area may be changed. A first insulating layer 111 may be located above the semiconductor layer).
Claim 6. Kang et al., disclose the display device according to claim 1, comprising a first routing area (item PA1) between the pad area and the link area; a second routing area (PA2) between the link area and the active area; a first contact hole (item 53) comprised in the first routing area; and a second contact hole (item 55) comprised in the second routing area are disposed to be vertically symmetrical with each other with reference to a virtual horizontal line present in the link area (as seen in the structure of fig. 8).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
5. Claim(s) 7-12, 16, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al., US 2021/0193775 A1, in view of Won, US 2019/0058028 A1.
Claim 7. Kang et al., disclose a display device (such as the one in fig. 8, [0098]), comprising:
-a display panel (item 100);
-and data lines disposed on the display panel, the data lines including a first data line, a second data line, and a third data line, comprise at least three data lines including the first, second, and third data lines disposed on different layers, respectively, while overlapping one another (this limitation would read through [0071] wherein is disclosed the first portion FL1 of each of the connection lines FL may be in parallel with the first data lines DL1, and part of the first portion FL1 may overlap the first data lines DL1, or the first portion FL1 may be adjacent to the first data lines DL1. The first portion FL1 of each of the connection lines FL may extend in parallel with the first data lines DL1 arranged as a plurality of columns. The second portion FL2 of each of the connection lines FL may be in parallel with the scan lines SL, and part of the second portion FL2 may overlap the scan lines SL, or the second portion FL2 may be adjacent to the scan lines SL. The second portion FL2 of each of the connection lines FL may extend in parallel with the scan lines SL arranged as a plurality of rows. The third portion FL3 of each of the connection lines FL may be in parallel with the second data lines DL2, and part of the third portion FL3 may overlap the second data lines DL2, or the third portion FL3 may be adjacent to the second data lines DL2. The third portion FL3 of each of the connection lines FL may extend in parallel with the second data lines DL2 arranged as a plurality of columns).
Kang et al., appear to not specify “wherein the data lines comprise data lines disposed in a zigzag form”.
However, in a similar display device, the structure of figs. 1 and 2 of Won, [0051] disclose a signal line area SLA, a bending area BA, and a panel pad area PPA are disposed in a non-display area N/A. On the other hand, the average width (for example, in the horizontal direction) of the display area A/A may be wider than the average width (for example, in the horizontal direction) of the non-display area N/A. More specifically, the non-display area N/A may be reduced in width away from the display area A/A and widened in the panel pad area PPA. It would have been prima facie obvious to have practiced well-known techniques to modify the device of Kang et al., using the structure from Won to fabricate a similar display device in a zigzag shape along the direction of the data line to optimize pixel layout, frequently in stereoscopic (3D) or high-resolution displays.
Claims 8-12, 16. Kang et al., disclose the display device according to claim 7, wherein: the first data line of the at least three data lines disposed on a lower layer includes a light shielding metal layer disposed on a substrate; the second data line of the at least three data lines disposed on a middle layer includes a first source/drain metal layer disposed on a lower insulating layer covering the light shielding metal layer; and the third data line of the at least three data lines disposed on an upper layer includes a second source/drain metal layer disposed on a middle insulating layer covering the first source/drain metal layer, wherein the middle layer is above the lower layer, and wherein the upper layer is above the middle layer.
This limitation would also read through [0102] wherein is disclosed the semiconductor layer of each of the first through seventh transistors T1 though T7 may include a source area and a drain area at both sides of the channel area. The semiconductor layer may include a source area S1 and a drain area D1 of the first transistor T1, a source area S2 and a drain area D2 of the second transistor T2, a source area S3 and a drain area D3 of the third transistor T3, a source area S4 and a drain area D4 of the fourth transistor T4, a source area S5 and a drain area D5 of the fifth transistor T5, a source area S6 and a drain area D6 of the sixth transistor T6, and a source area S7 and a drain area D7 of the seventh transistor T7. The source area or drain area may correspond to a source electrode or drain electrode of the transistor. In another exemplary embodiment, locations of the source area and the drain area may be changed. A first insulating layer 111 may be located above the semiconductor layer).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899