Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2020/0059435, hereinafter Yang) in view of Morozov et al. (US 2014/0019992, hereinafter Morozov).
Regarding claim 1, Yang discloses
A method comprising (fig. 1-11):
managing performance of a task on a message by a plurality of circuits of a processing device (paragraph [0038]: A plurality of sets of circuits may be cascaded together as a series of function circuits as the illustrated function circuits 0-n at references 154-158; paragraph [0041]: a general-purpose processor is cost efficient to run common high-level tasks such as task scheduling and data fusion. That is because a large number of applications require processors to run such high-level tasks, a general-purpose processor may be optimized to run the common high-level tasks efficiently), the task comprising a sequence of processings to be performed on the message and each circuit of the plurality of circuits performing a processing of the sequence of processings (paragraph [0038]: One data flow may follow one order of sets of function circuits while another data flow may follow a different order of sets of function circuits), the managing performance of the task comprising:
routing, based on the sequence of processings for the task (paragraph [0038]: One data flow may follow one order of sets of function circuits while another data flow may follow a different order of sets of function circuits), first information regarding the task to a first circuit of the plurality of circuits to perform a first processing (paragraph [0067]: At task box 2, the data blocks from the flow classifier 152 are provided to a set of circuits (function circuits 0 in this example), and the set of circuits processes data blocks of each data flow; paragraph [0065]: a source M at reference 118 is from the processor 104, and the processor 104 may have already assigned one or more flow IDs such as FIDM to the data blocks of the one or more data flow; paragraph [0074]: At task box 5, the processor 104 provides the information on the processor 104's processing of what is provided by the function circuits 0 to the next set of circuits (function circuits 1 at reference 156 in this example; paragraph [0078]: The operations in task boxes 3-5 continue to the next set of circuits until the data blocks of the data flows are processed by the series of sets of circuits for the data flows) of the sequence of processings on the message (paragraph [0038]: One data flow may follow one order of sets of function circuits while another data flow may follow a different order of sets of function circuits);
receiving, from … the first circuit, an output of the first processing (paragraph [0070]: At task box 3A, the function circuits 0 provide information on the processing of the data blocks of a data flow (e.g., data flow processing information) to the processor 104 based on the data flow's flow ID; paragraph [0078]: The operations in task boxes 3-5 continue to the next set of circuits until the data blocks of the data flows are processed by the series of sets of circuits for the data flows); and
routing, based on the sequence of processings identified for the task (paragraph [0038]: One data flow may follow one order of sets of function circuits while another data flow may follow a different order of sets of function circuits), second information regarding the task to a second circuit of the plurality of circuits to perform a second processing that follows the first processing (paragraph [0074]: At task box 5, the processor 104 provides the information on the processor 104's processing of what is provided by the function circuits 0 to the next set of circuits (function circuits 1 at reference 156 in this example); paragraph [0078]: The operations in task boxes 3-5 continue to the next set of circuits until the data blocks of the data flows are processed by the series of sets of circuits for the data flows) in the sequence of processings (paragraph [0038]: One data flow may follow one order of sets of function circuits while another data flow may follow a different order of sets of function circuits).
Yang does not explicitly disclose wherein each circuit of the plurality of circuits comprises one or more queues for output of tasks that are to be passed to one or more other circuits, and receiving, from a queue of the first circuit, an output of the first processing. Morozov discloses wherein each circuit of the plurality of circuits comprises one or more queues for output of tasks that are to be passed to one or more other circuits, and receiving, from a queue of the first circuit, an output of the first processing (paragraphs [0086], [0125], [0132]-[0133]: a plurality of processor units (i.e., circuits) configured to transfer processed data to other processor units; paragraph [0172]: the program thread adds the packet… to the packet queue packets_list in the Descriptor data structure of the ‘predecessor; paragraph [0185]: To transfer a packet to the ‘predecessor’, the fields of the respective packet_info structure are used to form a queue of packets; paragraphs [0193]-[0198]: “Receiving Packets from ‘Successors’ to Transfer to the System Output” by checking the queue, extracting the address of the queue elements, and receiving the processed packets from the queue). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit routing system of Yang to include one or more queues for the output of tasks at each circuit, such that the output of the first processing is received from a queue of the first circuit, as taught by Morozov. The motivation would have been to eliminate processing delays and wait times when passing processed data between parallel processing units, thereby ensuring the correct sequence of data streams is maintained efficiently without stalling the hardware circuits (Morozov paragraphs [0079]-[0080], [0108]).
Regarding claim 11 referring to claim 1, Yang discloses A method comprising: A non-transitory computer-readable storage medium for storing instructions executable by a processor, the instructions comprising: … (FIG. 10).
Regarding claim 20 referring to claim 1, Yang discloses A device comprising: a circuit configured to perform a method comprising … (FIG 4, 10).
Regarding claims 2 and 12, Yang discloses
wherein:
the method is performed by a controller (Fig. 4 (Control) Processor 104) communicatively coupled to each circuit of the plurality of circuits, wherein each circuit of the plurality of circuits (paragraph [0038]: A plurality of sets of circuits may be cascaded together as a series of function circuits as the illustrated function circuits 0-n at references 154-158) is connected to the controller via one or more interfaces (paragraph [0072]: The bus or interconnection 410 is between the processor 102 and the processor 104); and
routing to a circuit of the plurality of circuits comprises routing to an interface of the circuit from a queue of another circuit of the plurality of circuits (paragraph [0070]: At task box 3A, the function circuits 0 provide information on the processing of the data blocks of a data flow (e.g., data flow processing information) to the processor 104 based on the data flow's flow ID; paragraph [0071]: Alternatively, instead of task box 3A, at task box 3B, based on the data flow's flow ID, the function circuits 0 may provide information on the processing of the data blocks of the data flow to the next sets of circuits without providing the information to the processor 104).
Regarding claims 3 and 13, Yang discloses
wherein: the task is a first type of task, the first type of tasks comprising the sequence of processings performed with the plurality of circuits; and a second type of task comprises a second sequence of processings performed with at least some of the plurality of circuits, the second sequence of processings being different from the sequence of processings (paragraph [0038]: For example, flow 1 may be processed through the flow classifier 152-function circuits 0-function circuits 1-function circuits 2, while flow 2 may be processed through the flow classifier 152-function circuits 1-function circuits 2 (thus skipping function circuits 0). Additionally, flow 3 may be processed through the flow classifier 152-function circuits 2-function circuits 0 (thus skipping function circuits 1 and having the processing order between function circuits 0 and 2 reversed)).
Regarding claims 4 and 14, Yang discloses
wherein:
the task is one of a plurality of tasks, the plurality of tasks organized into at least a first flow of tasks (paragraph [0038]: One data flow may follow one order of sets of function circuits while another data flow may follow a different order of sets of function circuits. For example, flow 1 may be processed through the flow classifier 152-function circuits 0-function circuits 1-function circuits 2, while flow 2 may be processed through the flow classifier 152-function circuits 1-function circuits 2 (thus skipping function circuits 0). Additionally, flow 3 may be processed through the flow classifier 152-function circuits 2-function circuits 0 (thus skipping function circuits 1 and having the processing order between function circuits 0 and 2 reversed); paragraph [0041]: a general-purpose processor is cost efficient to run common high-level tasks such as task scheduling and data fusion);
managing performance of the task comprises selecting, at a time, between one or more tasks for which information is to be routed to circuits of the plurality of circuits for processing (paragraph [0038]: One data flow may follow one order of sets of function circuits while another data flow may follow a different order of sets of function circuits. For example, flow 1 may be processed through the flow classifier 152-function circuits 0-function circuits 1-function circuits 2, while flow 2 may be processed through the flow classifier 152-function circuits 1-function circuits 2 (thus skipping function circuits 0). Additionally, flow 3 may be processed through the flow classifier 152-function circuits 2-function circuits 0 (thus skipping function circuits 1 and having the processing order between function circuits 0 and 2 reversed); paragraph [0041]: a general-purpose processor is cost efficient to run common high-level tasks such as task scheduling and data fusion); and
managing performance of the task comprises ensuring that tasks of the first flow of tasks are processed by circuits of the plurality of circuits according to an order of the tasks in the first flow (paragraph [0038]: One data flow may follow one order of sets of function circuits while another data flow may follow a different order of sets of function circuits. For example, flow 1 may be processed through the flow classifier 152-function circuits 0-function circuits 1-function circuits 2, while flow 2 may be processed through the flow classifier 152-function circuits 1-function circuits 2 (thus skipping function circuits 0). Additionally, flow 3 may be processed through the flow classifier 152-function circuits 2-function circuits 0 (thus skipping function circuits 1 and having the processing order between function circuits 0 and 2 reversed)).
Regarding claims 5 and 15, Yang discloses
wherein:
the message comprises at least one of command or data (paragraph [0047] The processor 104 may provide two types of flow information to the processor 102. One type is flow mapping, which defines which source maps to which flow ID. The other type is flow configuration, which defines whether flow processing information of a set of circuits is to be provided to the processor 104 and how);
the task comprises a task description comprising information regarding performance of the task (paragraph [0049] The flow mapping information indicates how flow identifier are mapped to flows; paragraph [0053] The flow configuration is used by a set of circuits in the processor 102 to determine whether to provide flow processing information of a data flow to the processor 104 and how); and
routing the first information regarding the task to the first circuit (paragraph [0038]: One data flow may follow one order of sets of function circuits while another data flow may follow a different order of sets of function circuits; paragraph [0067]: At task box 2, the data blocks from the flow classifier 152 are provided to a set of circuits (function circuits 0 in this example), and the set of circuits processes data blocks of each data flow; paragraph [0065]: a source M at reference 118 is from the processor 104, and the processor 104 may have already assigned one or more flow IDs such as FIDM to the data blocks of the one or more data flow) and the second information regarding the task to the second circuit comprises routing, at a time, at least some of the task description at the time (paragraph [0074]: At task box 5, the processor 104 provides the information on the processor 104's processing of what is provided by the function circuits 0 to the next set of circuits (function circuits 1 at reference 156 in this example) … The information provided from the processor 104 to the function circuits 1 may be the updated data blocks of the data flow FIDL and/or one or more values. In one embodiment, the processor 104 provides one or more points/addresses of the information to the function circuits 1 (e.g., providing the one or more points/addresses to the bus or interconnect 410, from which the function circuits 1 retrieve)).
Regarding claims 6 and 16, Yang discloses
wherein:
each of the plurality of circuits is communicatively coupled to a shared memory (paragraph [0075]: when a data storage such as the data storage 116 is the source of a data flow, the processor 104 may provide the information on its processing such as updated data blocks back to the data storage. Since the data storage may provide its data blocks to a bus or interconnection such as the bus or interconnection 410, the updated data blocks are provided to the next set of circuits (the function circuits 1 in this example));
the at least one of command or the data for the message is stored in a message buffer in the shared memory (paragraph [0060]: Each data flow includes a stream of data; paragraph [0072]: The data blocks may be provided through a bus or an interconnect 410 … the data storage 116 may provide data blocks of data flows for the sets of circuits to process);
the information regarding performance of the task (paragraph [0047]: The processor 104 may provide two types of flow information to the processor 102. One type is flow mapping, which defines which source maps to which flow ID. The other type is flow configuration, which defines whether flow processing information of a set of circuits is to be provided to the processor 104 and how) is stored in the shared memory separate from the at least one of command or the data (paragraph [0060]: Each data flow includes a stream of data; paragraph [0072]: The data blocks may be provided through a bus or an interconnect 410 … the data storage 116 may provide data blocks of data flows for the sets of circuits to process); and
the task description comprises a pointer to a location storing the information regarding at least one of performance of the task, a pointer to the at least one of command or the data, or a flow identifier identifying a flow of tasks with which the task is associated (paragraph [0070]: the function circuits 0 provide information on the processing of the data blocks of a data flow (e.g., data flow processing information) to the processor 104 based on the data flow's flow ID … The updated data blocks or the processing results may be provided to the processor 104 through the function circuits 0 forwarding the updated data blocks or the processing results to the processor 104, or through the function circuits providing an address/pointer for the updated data blocks or the processing results for the processor 104 to retrieve).
Regarding claims 7 and 17, Yang discloses
wherein:
the first circuit edits the flow identifier for the task (paragraph [0080]: the processor 104 may update the flow mapping and flow configuration thus adjust the data flow processing at the processor 102; paragraph [0083]: the processor 104 instructs the processor 102 to update flow configuration of one or more sets of circuits at task box 2B; paragraph [0085]: Unlike the second approach, where the processor 104 may interact with a plurality of sets of circuits as a single module, in embodiments of the invention the processor 104 may interact with a set of circuits as necessary by updating the flow mapping of the flow identifier and/or flow configuration of the set of circuits); and
the second information regarding the task (paragraph [0074]: At task box 5, the processor 104 provides the information on the processor 104's processing of what is provided by the function circuits 0 to the next set of circuits (function circuits 1 at reference 156 in this example); paragraph [0078]: The operations in task boxes 3-5 continue to the next set of circuits until the data blocks of the data flows are processed by the series of sets of circuits for the data flows) has a different flow identifier for the task than the first information regarding the task (paragraph [0059]: At task box 1, the multiplexor 172 maps flow IDs to a plurality of data flows, each flow ID being mapped to one data flow. As discussed herein above, a source such as a camera may generate multiple data flows, and since each data flow is assigned to a flow ID, a source may be mapped to multiple flow IDs).
Regarding claims 8 and 18, Yang discloses
wherein routing the first and second information regarding the task to the first circuit and the second circuit, respectively, comprises looking up the flow identifier in a table of information regarding routing of tasks (paragraph [0096]: The flow configuration is included in a configuration table, where each entry of the configuration table corresponds to a flow ID in one embodiment; paragraph [0073]:At task box 4, the processor 104 processes the provided information on the processing of the data blocks of the data flow FIDL. The processing may be performed by an execution unit (not shown) of the processor 104; paragraph [0074]: At task box 5, the processor 104 provides the information on the processor 104's processing of what is provided by the function circuits 0 to the next set of circuits (function circuits 1 at reference 156 in this example); paragraph [0079]: through setting the flow mapping and/or flow configuration, the processor 104 may determine whether or not to involve in the processing of a data flow at one or more set of circuits and how).
Regarding claims 9 and 19, Yang discloses
wherein the first circuit is a programmable processing circuit (paragraph [0037]: A set of circuits may include an application-specific integrated circuit (ASIC) and/or a field programmable gate array (FPGA)).
Regarding claim 10, Yang discloses
further comprising: receiving the message from a network (paragraph [0033]: a source may be a data storage such as an illustrated data storage 116 … While the data storage 116 is illustrated within the processor 104, it may be outside of the processor 104 but coupled to the processor 104; paragraph [0109]: a source may be a camera, and the data flow includes images/video data captured by the camera (the data flow may be referred to as a visual data flow)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Takada (US 2017/0286018) discloses “the controller 2a switches the processor allocated to the private queue 20a from the processor 11c to the processor 11b (see a bold dotted arrow in FIG. 1) and switches the queue allocated with the processor 11c from the private queue 20a to the public queue 20b (see a bold solid arrow in FIG. 1)” (paragraph [0040]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in [0037] CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to [0037] CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISLEY N. KIM whose telephone number is (571)270-7832. The examiner can normally be reached M-F 11:30AM -7:30PM.
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/SISLEY N KIM/Primary Examiner, Art Unit 2196 09/04/2026
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