DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/03/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species 2 (claims 1-20) in the reply filed on 06/16/2026 is acknowledged.
Claims 1-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: WL3a, WL3b, WL4a, WL4b, 6-deck, 5-deck, 4-deck, 3-deck, 2-deck, and 1-deck. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-2, 4-11, and 14-19 are rejected under 35 U.S.C. 102(a)(1)(a)(2) as being anticipated by Kim (US Publication 20210375359).
Regarding independent claim 1, Kim teaches a semiconductor device (fig. 2, 100) comprising:
a substrate (110);
first to fourth word lines (fig. 7, WL1-WL4) extending in a first direction (x) that is parallel to a top surface of the substrate, and sequentially stacked over the substrate in a vertical direction perpendicular to the top surface of the substrate (fig. 7);
first to third bit lines (fig. 8B, BL_L1-BL_L3) extending in a second direction (fig. 7, y) that is parallel to the top surface of the substrate and crosses the first direction, and disposed between the first word line and the second word line, between the second word line and the third word line, and between the third word line and the fourth word line, respectively, in the vertical direction (fig. 8B);
first to sixth memory cells (fig. 11, D1-D6) disposed in an intersection region between the first word line and the first bit line, an intersection region between the first bit line and the second word line, an intersection region between the second word line and the second bit line, an intersection region between the second bit line and the third word line, an intersection region between the third word line and the third bit line, and an intersection region between the third bit line and the fourth word line, respectively (fig. 11);
first and second word line contacts (CP21, CP23, and VP in D1/D2) respectively connecting the first and second word lines to the substrate, and third and fourth word line contacts (VP in D3/D4 and D5/D6) respectively connecting the third and fourth word lines to the first and second word lines; and
first to third bit line contacts (fig. 14, CP13, CP33, CP53, and VP) respectively connecting the first to third bit lines to the substrate (fig. 14),
wherein, in a plan view, a first word line contact region where the first and third word line contacts are disposed, a second word line contact region where the second and fourth word line contacts are disposed, a first bit line contact region where the first bit line contact is disposed, a second bit line contact region where the second bit line contact is disposed, and a third bit line contact region where the third bit line contact is disposed are located at different positions (fig. 16).
Regarding dependent claim 2, Kim teaches the semiconductor device according to claim 1, wherein the first and third word lines are commonly activated, the second and fourth word lines are commonly activated, but they are activated independently of the first and third word lines (paragraph 0086), and the first to third bit lines are independently activated from each other (paragraph 0060).
Regarding dependent claims 4 and 16, Kim teaches the semiconductor device according to claim 1/claim 15, wherein, in the first direction, each of the first and third word lines is divided into a plurality of segments (fig. 11), and the plurality of segments of each of the first and third word lines are spaced apart from each other with the second and fourth word line contacts interposed therebetween (fig. 11), and
in the first direction, each of the second and fourth word lines is divided into a plurality of segments (fig. 11), and the plurality of segments of each of the second and fourth word lines are spaced apart from each other with the first and third word line contacts interposed therebetween in a plan view (fig. 11).
Regarding dependent claims 5 and 18, Kim teaches the semiconductor device according to claim 1/claim 15, wherein, in the second direction, the first bit line is divided into a plurality of segments (fig. 14), and the plurality of segments of the first bit line are spaced apart from each other with the second bit line contact and the third bit line contact interposed therebetween (fig. 14),
in the second direction, the second bit line is divided into a plurality of segments (fig. 14), and the plurality of segments of the second bit line are spaced apart from each other with the third bit line contact interposed therebetween (fig. 14), and
in the second direction, the third bit line is divided into a plurality of segments (fig. 14), and the plurality of segments of the third bit line are spaced apart from each other with respect to the second bit line contact interposed therebetween in a plan view (fig. 14).
Regarding dependent claim 6, Kim teaches the semiconductor device according to claim 1, wherein the substrate includes a plurality of tiles (fig. 2, MAT) arranged in the first direction and the second direction, and
the first word line contact region, the second word line contact region, the first bit line contact region, the second bit line contact region, and the third bit line contact region are located in different tiles (fig. 16).
Regarding dependent claim 7, Kim teaches the semiconductor device according to claim 6, wherein, in each of the first direction and the second direction, any one of the first and second word line contact regions and any one of the first to third bit line contact regions are alternately arranged (fig. 16).
Regarding dependent claim 8, Kim teaches the semiconductor device according to claim 7, wherein, in the first direction, the first word line contact region and the second word line contact region are alternately arranged (fig. 11).
Regarding dependent claim 9, Kim teaches the semiconductor device according to claim 7, wherein, in the second direction, the first bit line contact region is alternately arranged with any one of the second and third bit line contact regions, and the second bit line contact region and the third bit line contact region are alternately arranged (fig. 14).
Regarding dependent claim 10, Kim teaches the semiconductor device according to claim 8, wherein, in the first direction, each of the first and third word lines is divided into a plurality of segments (fig. 11), and the plurality of segments of each of the first and third word lines are spaced apart from each other with the second and fourth word line contacts interposed therebetween (fig. 11),
in the first direction, each of the second and fourth word lines is divided into a plurality of segments (fig. 11), and the plurality of segments of each of the second and fourth word lines are spaced apart from each other with the first and third word line contacts interposed therebetween, in a plan view (fig. 11),
the second and fourth word line contacts overlap each other and the first and third word line contacts overlap each other (fig. 11), and a length of each segment of each of the first and third word lines is substantially the same as a length of each segment of each of the second and fourth word lines (fig. 11).
Regarding dependent claim 11, Kim teaches the semiconductor device according to claim 9, wherein, in the second direction, the first bit line is divided into a plurality of segments (fig. 14), and the plurality of segments of the first bit line are spaced apart from each other with the second bit line contact and the third bit line contact that are interposed therebetween (fig. 14),
in the second direction, the second bit line is divided into a plurality of segments (fig. 14), and the plurality of segments of the second bit line are spaced apart from each other with the third bit line contact interposed therebetween (fig. 14),
in the second direction, the third bit line is divided into a plurality of segments (fig. 14), and the plurality of segments of the third bit line are spaced apart from each other with respect to the second bit line contact interposed therebetween in a plan view (fig. 14), and
a length of each segment of the second bit line and a length of each segment of the third bit line are twice a length of each segment of the first bit line (fig. 13).
Regarding independent claim 14, Kim teaches a semiconductor device (fig. 2, 100) comprising:
a substrate (110) including a plurality of tiles (MAT) arranged in a first direction (x) and a second direction (y), the first and the second direction being parallel to a top surface of the substrate and crossing each other (fig. 2), the substrate further including first and second word line contact regions and first to third bit line contact regions that are arranged in different tiles (fig. 16);
first to fourth word lines (fig. 7, WL1-WL4) extending in the first direction and sequentially stacked over the substrate in a vertical direction perpendicular to the top surface of the substrate (fig. 7);
first, second, and third bit lines (fig. 8B, BL_L1-BL_L3) extending in the second direction, and disposed between the first word line and the second word line, between the second word line and the third word line, and the third word line and the fourth word line, respectively, in the vertical direction (fig. 8B);
first to sixth memory cells (fig. 11, D1-D6) disposed in an intersection region between the first word line and the first bit line, an intersection region between the first bit line and the second word line, an intersection region between the second word line and the second bit line, an intersection region between the second bit line and the third word line, an intersection region between the third word line and the third bit line, and an intersection region between the third bit line and the fourth word line, respectively (fig. 11);
first and third word line contacts (CP21, CP23, and VP in D3/D4) connecting the first and third word lines to the first word line contact region of the substrate (fig. 11);
second and fourth word line contacts (VP in D1/D2 and VP in D5/D6) connecting the second and fourth word lines to the second word line contact region of the substrate (fig. 11); and
first to third bit line contacts (fig. 14, CP13, CP33, CP53, and VP) respectively connecting the first to third bit lines to the first to third bit line contact regions of the substrate (fig. 14).
Regarding dependent claim 15, Kim teaches the semiconductor device according to claim 14, wherein, in each of the first direction and the second direction, any one of the first and second word line contact regions and any one of the first to third bit line contact regions are alternately arranged (fig. 16),
in the first direction, the first word line contact region and the second word line contact region are alternately arranged (fig. 16), and
in the second direction, the first bit line contact region is alternately arranged with any one of the second and third bit line contact regions, and the second bit line contact region and the third bit line contact region are alternately arranged (fig. 16).
Regarding dependent claim 17, Kim teaches the semiconductor device according to claim 16, wherein a length of each segment of each of the first and third word lines is substantially the same as a length of each segment of each of the second and fourth word lines (fig. 11).
Regarding dependent claim 19, Kim teaches the semiconductor device according to claim 18, wherein a length of each segment of the second bit line and a length of each segment of the third bit line are twice a length of each segment of the first bit line (fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim.
Regarding dependent claims 3 and 20, Kim teaches the semiconductor device according to claim 1/claim 14.
Kim does not explicitly teach wherein the first memory cell is selected by the first and third word lines and the first bit line, the second memory cell is selected by the second and fourth word lines and the first bit line, the third memory cell is selected by the second and fourth word lines and the second bit line, the fourth memory cell is selected by the first and third word lines and the second bit line, the fifth memory cell is selected by the first and third word lines and the third bit line, and the sixth memory cell is selected by the second and fourth word lines and the third bit line, however, Kim discloses a global word line selection switch and a global bit line selection switch, which selects specific local word lines/local bit lines in response to a selection signal (paragraph 0062-0063).
Therefore, each memory cell can be selected by the specified word line and bit line combinations listed above (Ex parte Masham, 2 USPQ2d 1647 (1987). See MPEP 2144, It has been held that a recitation with respect to the way a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kwon (US Publication 20210098062).
Regarding dependent claim 12, Kim teaches the semiconductor device according to claim 6.
Kim does not teach wherein each of the first and second word line contact regions has a shape in which a length in the second direction is greater than a length in the first direction in a corresponding tile, and is located at a central region of the corresponding tile in the first direction.
Kwon teaches wherein each of the first and second word line contact regions (fig. 8, 116, 117, 126, and 127) has a shape in which a length in the second direction is greater than a length in the first direction in a corresponding tile, and is located at a central region of the corresponding tile in the first direction (fig. 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kim and the contact regions of Kwon to improve the performance of the memory device (Kwon paragraph 0078).
Regarding dependent claim 13, Kim teaches the semiconductor device according to claim 6.
Kim does not teach wherein each of the first to third bit line contact regions has a shape in which a length in the first direction is greater than a length in the second direction in a corresponding tile, and is located at a central region of the corresponding tile in the second direction.
Kwon teaches wherein each of the first to third bit line contact regions (fig. 8, 113, 115, and 123) has a shape in which a length in the first direction is greater than a length in the second direction in a corresponding tile, and is located at a central region of the corresponding tile in the second direction (fig. 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kim and the contact regions of Kwon to improve the performance of the memory device (Kwon paragraph 0078).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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