DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The disclosure is objected to because of the following informalities: the specification uses the term “semiconductor dielectric” throughout the disclosure. It is unclear what “semiconductor dielectric” means. The “semiconductor dielectric” pattern is disclosed as being an air gap surrounded laterally by sidewall dielectric patterns with an upper and lower capping pattern on the sidewall dielectric patterns. There is no discussion that indicates what component in the “semiconductor dielectric” pattern comprises a semiconductor. “Semiconductor dielectric” is non-sensical in that it isn’t clear in what is “semiconductor” about the pattern. The structure claimed only mentions dielectric materials. Examiner believes that using just the term “dielectric” pattern instead of “semiconductor dielectric” pattern would eliminate the confusion.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities: in lines 13-14, "between the semiconductor patterns" should be amended to read -between each of the . Appropriate correction is required.
Claim 2 is objected to because of the following informalities: "the semiconductor patterns" should be amended to read -adjacent semiconductor patterns of the plurality of semiconductor patterns-. Appropriate correction is required.
Claim 11 is objected to because of the following informalities: on page 25, lines 7-8, "between the semiconductor patterns" should be amended to read -between each of the plurality of semiconductor patterns along the first direction-. Appropriate correction is required.
Claim 12 is objected to because of the following informalities: in line 18, "a metal oxide" should be amended to read -the metal oxide-. Appropriate correction is required.
Claim 14 is objected to because of the following informalities: in line 26, "the semiconductor patterns" should be amended to read -adjacent semiconductor patterns of the plurality of semiconductor patterns-. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: in line 17, "a semiconductor pattern" should be amended to read -a plurality of semiconductor patterns-. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: in line 17, “is spaced” should be amended to -are spaced-. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: in line 18, “each of the semiconductor patterns” should be amended to -each of the plurality of semiconductor patterns-. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: in line 26, “each of the semiconductor patterns” should be amended to -each of the plurality of semiconductor patterns-. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: on page 27, line 3, "wherein the" should be amended to read -wherein each of the-. Appropriate correction is required.
Claim 20 is objected to because of the following informalities: in line 14, "the semiconductor patterns" should be amended to read -adjacent semiconductor patterns of the plurality of semiconductor patterns-. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 10, 11, 18, and 19 use the term “semiconductor dielectric” pattern. It is unclear what “semiconductor dielectric” means. Claims 1 and 19 recite that the “semiconductor dielectric” pattern comprises an air gap and sidewall dielectric patterns with an upper and lower capping pattern on the sidewall dielectric patterns. There is no limitation in the claims that indicate what component in the “semiconductor dielectric” pattern comprises a semiconductor. “Semiconductor dielectric” is non-sensical in that it isn’t clear in what is “semiconductor” about the pattern. The structure claimed only mentions dielectric materials. The specification provides no indication either of what is “semiconductor” about the “semiconductor dielectric” pattern. Examiner believes that using just the term “dielectric” pattern instead of “semiconductor dielectric” pattern would eliminate the confusion and interprets the term “semiconductor dielectric” to mean -dieletric-. Claims 2-10, 12-18, and 20 inherit the deficiencies of their respective independent claim. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 8-14 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2022/0102352 and Lee hereinafter) in view of Pulugurtha et al (US 2015/0243748 and Pulugurtha hereinafter).
As to claims 1-6 and 8-10: Lee discloses [claim 1] a semiconductor memory device (Figs. 4A and 4B; [0021]; [0064]), comprising: a bit line (BL; [0067]) that extends in a first direction (D1; [0070]); a plurality of semiconductor patterns (CP; [0069]) disposed on the bit line (BL) and that are spaced apart from each other in the first direction (D1), wherein each of the semiconductor patterns (CP) includes a first vertical part (left vertical part of CP in each “cell”), a second vertical part (right vertical part of CP in each “cell”) opposite to the first vertical part (left vertical part of CP in each “cell”) in the first direction (D1), and a horizontal part (horizontal part of CP in each “cell”) that connects the first (left vertical part of CP in each “cell”) and second (right vertical part of CP in each “cell”) vertical parts to each other; a first word line (WL1; [0069]) and a second word line (WL2; [0069]) that are disposed on the horizontal part and respectively adjacent to the first vertical part (left vertical part of CP in each “cell”) and the second vertical part (right vertical part of CP in each “cell”); and a semiconductor dielectric pattern (115; [0072]) disposed on the bit line (BL) and interposed between the semiconductor patterns (CP); [claim 9] further comprising a gate dielectric pattern (Gox; [0085]) interposed between the first vertical part (left vertical part of CP in each “cell”) and the first word line (WL1) and between the second vertical part (right vertical part of CP in each “cell”) and the second word line (WL2); [claim 10] wherein the gate dielectric pattern (Gox) is spaced apart from the semiconductor dielectric pattern (115).
Lee fails to expressly disclose [claim 1] wherein the semiconductor dielectric pattern includes: a lower capping pattern; a plurality of sidewall dielectric patterns disposed on the lower capping pattern and that are spaced apart from each other in the first direction; an air gap interposed between the sidewall dielectric patterns; and an upper capping pattern disposed on the sidewall dielectric patterns, wherein a height of top surfaces of the sidewall dielectric patterns is a same as a height of top surfaces of the first and second vertical parts; [claim 2] wherein the sidewall dielectric patterns are correspondingly interposed between the air gap and the semiconductor patterns; [claim 3] wherein the sidewall dielectric patterns include metal oxide; [claim 4] wherein the sidewall dielectric patterns include at least one of hafnium (Hf) oxide, silicon (Si) oxide, aluminum (Al) oxide, zirconium (Zr) oxide, titanium (Ti) oxide, tantalum (Ta) oxide, niobium (Nb) oxide, lanthanum (La) oxide, barium (Ba) oxide, strontium (Sr) oxide, yttrium (Y) oxide, or ruthenium (Lu) oxide; [claim 5] wherein the sidewall dielectric patterns are in direct contact with corresponding semiconductor patterns; [claim 6] wherein the air gap is surrounded by the lower capping pattern, the upper capping pattern, and the sidewall dielectric patterns; [claim 8] wherein the lower capping pattern is in direct contact with a top surface of the bit line.
Lee discloses a memory structure with vertical channel transistors VCT ([0069]) with insulating structures 115 between adjacent VCT ([0072]).
Pulugurtha discloses in Figs. 1G and 1H a structure with vertical channel transistors ([0020]) having U-shaped semiconductor patterns comprises 132 and 144 ([0051]) separated from word lines 118 ([0030]) by a dielectric 116 ([0030]). The vertical channel transistors have an insulating structure 140 ([0056]) therebetween [claim 1] wherein the semiconductor dielectric pattern (Fig. 1H; 140; [0056]) includes: a lower capping pattern (bottom portion of 140 below 152, claim doesn’t state that the capping patterns and sidewall dielectric patterns comprise different materials, therefore, Examiner interprets they can comprise the same material; [0056]); a plurality of sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) disposed on the lower capping pattern (bottom portion of 140 below 152) and that are spaced apart from each other in the first direction (the vertical portions of 140 adjacent to the air gap 152 are spaced apart from each other in the first direction; claim doesn’t state that the entirety of each sidewall dielectric pattern is spaced apart from the adjacent sidewall dielectric pattern); an air gap (152; [0056]) interposed between the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152); an upper capping pattern (upper portion of 140 that is directly over 152) disposed on (the upper portion of 140 that is directly over 152 is on the vertical sidewall of the portion of 140 identified as the sidewall dielectric patterns) the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152); wherein a height of top surfaces (142; [0048]) of the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) is a same as a height of top surfaces (top of 144/136; [0053]) of the first and second vertical parts (comprising 144 and vertical portions of 132; [0053]); [claim 2] wherein the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) are correspondingly interposed between the air gap (152) and the semiconductor patterns (comprising 144 and 132; [0053]); [claim 3] wherein the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) include metal oxide (140 can comprise aluminum oxide; [0047]); [claim 4] wherein the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) include at least one of hafnium (Hf) oxide, silicon (Si) oxide, aluminum (Al) oxide, zirconium (Zr) oxide, titanium (Ti) oxide, tantalum (Ta) oxide, niobium (Nb) oxide, lanthanum (La) oxide, barium (Ba) oxide, strontium (Sr) oxide, yttrium (Y) oxide, or ruthenium (Lu) oxide (140 can comprise aluminum oxide; [0047]); [claim 5] wherein the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) are in direct contact with corresponding semiconductor patterns (comprising 144 and 132); [claim 6] wherein the air gap (152) is surrounded by the lower capping pattern, the upper capping pattern, and the sidewall dielectric patterns (140).
As to [claim 8] wherein the lower capping pattern is in direct contact with a top surface of the bit line, when the isolation structure 140 in Fig. 1H of Pulugurtha is substituted into Lee to replace 115, the lower capping pattern of Pulugurtha will be adjacent to the bit line BL in Fig. 4B.
Therefore, the claimed invention would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because the substitution of one known element (an isolation structure comprising an air gap surrounded by a metal oxide dielectric material as shown in Fig. 1H of Pulugurtha) for another (a solid material of metal oxide dielectric material as shown in Fig. 1G of Pulugurtha and Fig. 4B of Lee) would have yielded predictable results (reducing cross-talk between neighboring vertical transistors, limit capacitance, and increase shorts margin between adjacent word lines ([0057]) of Pulugurtha) to one of ordinary skill in the art before the effective filing date of the claimed invention. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
As to claims 11-14 and 17-18: Lee discloses [claim 11] a semiconductor memory device (Figs. 4A and 4B; [0021]; [0064]), comprising: a bit line (BL; [0067]) that extends in a first direction (D1; [0070]); a plurality of semiconductor patterns (CP; [0069]) disposed on the bit line (BL) and that are spaced apart from each other in the first direction (D1), wherein each of the semiconductor patterns (CP) includes a first vertical part (left vertical part of CP in each “cell”), a second vertical part (right vertical part of CP in each “cell”) opposite to the first vertical part (left vertical part of CP in each “cell”) in the first direction (D1), and a horizontal part (horizontal part of CP in each “cell”) that connects the first (left vertical part of CP in each “cell”) and second (right vertical part of CP in each “cell”) vertical parts to each other; a first word line (WL1; [0069]) and a second word line (WL2; [0069]) that are disposed on the horizontal part and respectively adjacent to the first vertical part (left vertical part of CP in each “cell”) and the second vertical part (right vertical part of CP in each “cell”); a plurality of landing pads (LP; [0094]) disposed on the first (left vertical part of CP in each “cell”) and second (right vertical part of CP in each “cell”) vertical parts; and a semiconductor dielectric pattern (115; [0072]) disposed on the bit line (BL) and interposed between the semiconductor patterns (CP); [claim 17] further comprising a gate dielectric pattern (Gox; [0085]) interposed between the first vertical part (left vertical part of CP in each “cell”) and the first word line (WL1) and between the second vertical part (right vertical part of CP in each “cell”) and the second word line (WL2); [claim 18] wherein the gate dielectric pattern (Gox) is spaced apart from the semiconductor dielectric pattern (115).
Lee fails to expressly disclose [claim 11] wherein the semiconductor dielectric pattern includes an air gap and a barrier pattern that surrounds the air gap, and wherein a sidewall of the barrier pattern includes a metal oxide; [claim 12] wherein the barrier pattern includes: an upper capping pattern adjacent to the landing pads; a lower capping pattern adjacent to the bit line; and a sidewall dielectric pattern that connects the upper capping pattern to the lower capping pattern, wherein the sidewall dielectric pattern includes a metal oxide; [claim 13] wherein the metal oxide includes at least one of hafnium (Hf) oxide, silicon (Si) oxide, aluminum (Al) oxide, zirconium (Zr) oxide, titanium (Ti) oxide, tantalum (Ta) oxide, niobium (Nb) oxide, lanthanum (La) oxide, barium (Ba) oxide, strontium (Sr) oxide, yttrium (Y) oxide, or ruthenium (Lu) oxide; [claim 14] wherein the barrier pattern is in direct contact with the semiconductor patterns.
Lee discloses a memory structure with vertical channel transistors VCT ([0069]) with insulating structures 115 between adjacent VCT ([0072]).
Pulugurtha discloses in Figs. 1G and 1H a structure with vertical channel transistors ([0020]) having U-shaped semiconductor patterns comprises 132 and 144 ([0051]) separated from word lines 118 ([0030]) by a dielectric 116 ([0030]). The vertical channel transistors have an insulating structure 140 ([0056]) therebetween [claim 11] wherein the semiconductor dielectric pattern (Fig. 1H; 140; [0056]) includes an air gap (152; [0056]) and a barrier pattern (material portions of 140) that surrounds the air gap (152), and wherein a sidewall of the barrier pattern (material portions of 140) includes a metal oxide (140 can comprise aluminum oxide; [0047]); [claim 12] wherein the barrier pattern (material portions of 140) includes: an upper capping pattern (upper portion of 140); a lower capping pattern (bottom portion of 140); and a sidewall dielectric pattern (vertical portions of 140 adjacent to the air gap 152) that connects the upper capping pattern (upper portion of 140) to the lower capping pattern (lower portion of 140), wherein the sidewall dielectric pattern (vertical portions of 140 adjacent to the air gap 152) includes a metal oxide (140 can comprise aluminum oxide; [0047]); [claim 13] wherein the metal oxide (140 can comprise aluminum oxide; [0047]) includes at least one of hafnium (Hf) oxide, silicon (Si) oxide, aluminum (Al) oxide, zirconium (Zr) oxide, titanium (Ti) oxide, tantalum (Ta) oxide, niobium (Nb) oxide, lanthanum (La) oxide, barium (Ba) oxide, strontium (Sr) oxide, yttrium (Y) oxide, or ruthenium (Lu) oxide (140 can comprise aluminum oxide; [0047]); [claim 14] wherein the barrier pattern (material portions of 140) is in direct contact with the semiconductor patterns (132).
As to [claim 12] where the upper capping pattern is adjacent to the landing pads and the lower capping pattern is adjacent to the bit line, when the isolation structure 140 in Fig. 1H of Pulugurtha is substituted into Lee to replace 115, the upper capping pattern of Pulugurtha will be adjacent to the landing pads LP and the lower capping pattern of Pulugurtha will be adjacent to the bit line BL in Fig. 4B.
Therefore, the claimed invention would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because the substitution of one known element (an isolation structure comprising an air gap surrounded by a metal oxide dielectric material as shown in Fig. 1H of Pulugurtha) for another (a solid material of metal oxide dielectric material as shown in Fig. 1G of Pulugurtha and Fig. 4B of Lee) would have yielded predictable results (reducing cross-talk between neighboring vertical transistors, limit capacitance, and increase shorts margin between adjacent word lines ([0057]) of Pulugurtha) to one of ordinary skill in the art before the effective filing date of the claimed invention. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
As to claims 19 and 20: Lee discloses [claim 19] a semiconductor memory device (Figs. 4A and 4B; [0021]; [0064]), comprising: a plurality of bit lines (BL; [0067]) that extend in a first direction (D1; [0070]), wherein the bit lines (BL) are spaced apart from each other in a second direction (D2) that is orthogonal to the first direction (D1); a semiconductor pattern (CP; [0069]) disposed on each of the bit lines (BL) and that is spaced apart from each other in the first direction (D1), wherein each of the semiconductor patterns (CP) includes a first vertical part (left vertical part of CP in each “cell”), a second vertical part (right vertical part of CP in each “cell”) opposite to the first vertical part (left vertical part of CP in each “cell”) in the first direction (D1), and a horizontal part (horizontal part of CP in each “cell”) that connects the first (left vertical part of CP in each “cell”) and second (right vertical part of CP in each “cell”) vertical parts to each other; a first word line (WL1; [0069]) and a second word line (WL2; [0069]) that are disposed on the horizontal part and respectively adjacent to the first vertical part (left vertical part of CP in each “cell”) and the second vertical part (right vertical part of CP in each “cell”); a gate dielectric pattern (Gox; [0085]) interposed between the first vertical part (left vertical part of CP in each “cell”) and the first word line (WL1) and between the second vertical part (right vertical part of CP in each “cell”) and the second word line (WL2); a plurality of semiconductor dielectric patterns (115; [0072]) respectively disposed on each of the bit lines (BL) and interposed between the semiconductor patterns (CP), wherein the semiconductor dielectric patterns (115) are in direct contact with the bit lines (BL); a plurality of landing pads (LP; [0094]) disposed on the first (left vertical part of CP in each “cell”) and second (right vertical part of CP in each “cell”) vertical parts; and a plurality of data storage patterns (DSP; [0069]) respectively disposed on corresponding landing pads (LP).
Lee fails to expressly disclose [claim 19] wherein the semiconductor dielectric patterns include: a lower capping pattern; a plurality of sidewall dielectric patterns disposed on the lower capping pattern; an air gap formed between the sidewall dielectric patterns; and an upper capping pattern disposed on the sidewall dielectric patterns, wherein top surfaces of the sidewall dielectric patterns are at a same height as top surfaces of the first and second vertical parts of the semiconductor pattern; wherein the sidewall dielectric patterns include a metal oxide; [claim 20] wherein the sidewall dielectric patterns are in direct contact with the semiconductor patterns.
Lee discloses a memory structure with vertical channel transistors VCT ([0069]) with insulating structures 115 between adjacent VCT ([0072]).
Pulugurtha discloses in Figs. 1G and 1H a structure with vertical channel transistors ([0020]) having U-shaped semiconductor patterns comprises 132 and 144 ([0051]) separated from word lines 118 ([0030]) by a dielectric 116 ([0030]). The vertical channel transistors have an insulating structure 140 ([0056]) therebetween [claim 19] wherein the semiconductor dielectric patterns (Fig. 1H; 140; [0056]) include: a lower capping pattern (bottom portion of 140 below 152, claim doesn’t state that the capping patterns and sidewall dielectric patterns comprise different materials, therefore, Examiner interprets they can comprise the same material; [0056]); a plurality of sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) disposed on the lower capping pattern (bottom portion of 140 below 152); an air gap (152; [0056]) formed between the sidewall dielectric patterns (the vertical portions of 140 adjacent to the air gap 152 are spaced apart from each other in the first direction); and an upper capping pattern (upper portion of 140 that is directly over 152) disposed on (the upper portion of 140 that is directly over 152 is on the vertical sidewall of the portion of 140 identified as the sidewall dielectric patterns) the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152), wherein top surfaces (142; [0048]) of the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) are at a same height as top surfaces (top of 144/136; [0053]) of the first and second vertical parts (comprising 144 and vertical portions of 132; [0053]) of the semiconductor pattern (comprising 144 and 132), and wherein the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) include a metal oxide (140 can comprise aluminum oxide; [0047]); [claim 20] wherein the sidewall dielectric patterns (vertical portions of 140 that extend from the bottom of 152 to the top of 140 that is not directly over 152) are in direct contact with the semiconductor patterns (comprising 144 and 132).
As to [claim 19] wherein the lower capping pattern is disposed on each of the bit lines, when the isolation structure 140 in Fig. 1H of Pulugurtha is substituted into Lee to replace 115, the lower capping pattern of Pulugurtha will be adjacent to the bit line BL in Fig. 4B.
Therefore, the claimed invention would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because the substitution of one known element (an isolation structure comprising an air gap surrounded by a metal oxide dielectric material as shown in Fig. 1H of Pulugurtha) for another (a solid material of metal oxide dielectric material as shown in Fig. 1G of Pulugurtha and Fig. 4B of Lee) would have yielded predictable results (reducing cross-talk between neighboring vertical transistors, limit capacitance, and increase shorts margin between adjacent word lines ([0057]) of Pulugurtha) to one of ordinary skill in the art before the effective filing date of the claimed invention. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Allowable Subject Matter
Claims 7, 15, and 16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
3/23/2026
Prosecution Insights