DETAILED ACTION
This Office action responds to the application filed on 11/06/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 1 is objected to because of the following informalities:
The limitation “a coreless substrate” in line 2 is repeated in line 3 “a package device mounted on a coreless substrate.” The first mention of a coreless substrate is sufficient to establish antecedent basis and does not need to be repeated.
An interpretation of the limitations of Claim 1 are construed in order to further examination.
a coreless substrate;
a package device mounted on the coreless substrate”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 & 10-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230005808) in view of Yu (US 20210327866).
Regarding Claim 1, Tsai (see, e.g., fig. 7, annotated figure 7) shows a coreless substrate package, comprising:
a coreless substrate 100;
a package device 101a-b mounted on a coreless substrate,
wherein the package device comprises a function die,
wherein the function silicon die has an active front side (bottom side, see, e.g., annotated figure 7) facing downwardly to the coreless substrate,
and an exposed, passive rear side 101a-bs opposite to the active front side,
wherein the package device further comprises an encapsulant 102 covering peripheral sidewalls of the function die;
an underfill material UF filling into a space between the package device and the coreless substrate;
a stiffener ring 260 disposed on a top surface of the coreless substrate along perimeter of the coreless substrate;
and a gap fill material 200 disposed in a gap G between the stiffener ring and the package device.
Tsai, however, fails to show
a function silicon die
Yu (see, e.g., fig. 1a, para.0021), in a similar device to Tsai, teaches a die comprising silicon as a substrate is an obvious and suitable material for the die.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the die comprising silicon as a substrate of Yu in the device of Tsai as an obvious and suitable material for the die.
Regarding Claim 10, Tsai (see, e.g., para.0042, para.0046), in view of Yu, shows the coreless substrate package according to claim 1,
wherein the coreless substrate does not include a permanent core structure (see, e.g., para.0042, para.0046).
Regarding Claim 11, Tsai (see, e.g., fig. 7), in view of Yu, shows the coreless substrate package according to claim 1,
wherein the stiffener ring is coplanar with the package device and is affixed onto the top surface of the coreless substrate by using an adhesive layer 262 (see, e.g., para.0051).
Regarding Claim 12, Tsai, in view of Yu, shows the coreless substrate package according to claim 1,
wherein the gap fill material 200 comprises a molding compound (see, e.g., para.0048-0049).
Regarding Claim 13, Tsai, in view of Yu, shows the coreless substrate package according to claim 1,
wherein the gap fill material 200 and the underfill material UF have different compositions (see, e.g., para.0058).
Regarding Claim 14, Tsai (see, e.g., fig. 7), in view of Yu, shows the coreless substrate package according to claim 1,
wherein the gap fill material 200 and the encapsulant 102 have different compositions (see, e.g., para.0047, para.0054).
Regarding Claim 16, Tsai, in view of Yu, shows the coreless substrate package according to claim 1,
wherein the package device 10 comprises a Chip-on-Wafer package or a fan-out package (see, e.g., para.0047).
Regarding Claim 17, Tsai, in view of Yu, shows the coreless substrate package according to claim 1,
wherein the function silicon die 10 comprises a System on Chip (SoC) die, an RF die, or an application processor (AP) die (see, e.g., para.0047).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230005808) in view of Yu (US 20210327866) and further in view of Sain (US 20210296241).
Regarding Claim 2, Tsai, in view of Yu, shows the coreless substrate package according to claim 1,
Tsai, in view of Yu, however, fails to show
wherein the coreless substrate has a dimension of greater than 45mm × 45mm.
However, ranges of substrate dimension will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Sain (see, e.g., fig. 1, para.0024), in a similar device to Tsai, in view of Yu, shows a coreless substrate with dimension of 60mm × 60mm. Since the applicant has not established the criticality (see next paragraph below) of the claimed range, and similar ranges have been used in the art, it would have been obvious to one of ordinary skill in the art to use the ranges of the coreless substrate of Sain in the device of Tsai, in view of Yu.
Criticality
The specification contains no disclosure of either the critical nature of the claimed temperature and pressure ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230005808) in view of Yu (US 20210327866) and further in view of Yeh (US 20230402402).
Regarding Claim 3, Tsai, in view of Yu, shows the coreless substrate package according to claim 1,
Tsai, in view of Yu, however, fails to show
wherein a distance between an inner sidewall surface of the stiffener ring and a sidewall surface of the package device is not less than 10 mm.
However, ranges of distance will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ranges are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Yeh (see, e.g., figs. 4a-b, para.0022) in a device similar to Tsai, in view of Yu, shows a distance D4 between an inner sidewall surface of the stiffener ring 58 and a sidewall surface of the package device 50a can be between 1.5 mm and 20 mm. Since the applicant has not established the criticality of the claimed range, and similar ranges have been used in the art, it would have been obvious to one of ordinary skill in the art to use the ranges of distance of Yeh in the device of Tsai, in view of Yu. See paragraph 24 for criticality statement.
Claims 4, 7, 8 & 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230005808) in view of Yu (US 20210327866) and further in view of Hu (US 9543249).
Regarding Claim 4, Tsai, in view of Yu, shows the coreless substrate package according to claim 1,
wherein the coreless substrate comprises at least one insulating layer and conductive layers in the at least one insulating layer (see, e.g., para.0046).
Tsai (see, e.g., para.0046), in view of Yu, states the coreless substrate 100 can contain traces and interconnections.
The drawings of Tsai, in view of Yu, however, fail to explicitly show a configuration for the traces and interconnections of coreless substrate 100.
Although Sun does not explicitly show a configuration for coreless substrate, Hu (see, e.g., fig. 6, para.0033-0035), shows a configuration for a coreless substrate including at least one insulating layer D10-30 and conductive layers 611, 622, & 633 in the at least one insulating layer
Therefore it would have been obvious at the time of filing the invention to one of ordinary skill in the art to interpret the coreless substrate of Tsai, in view of Yu, as shown in the configuration of Hu.
Regarding Claim 7, Tsai, in view of Yu and further in view of Hu (see, e.g., fig. 6, para.0033, para.0036). shows the coreless substrate package according to claim 4,
wherein the conductive layers comprise connection pads 10T (see, e.g., para.0033) exposed from the top surface of the coreless substrate and ball grid array (BGA) ball pads 30B (see, e.g., para.0036) disposed at a bottom surface of the coreless substrate.
Regarding Claim 8 Tsai (see, e.g., fig. 7, para.0047-0048), in view of Yu and further in view of Hu. The coreless substrate package according to claim 7,
wherein the package device is mounted on the top surface of the coreless substrate in a flip-chip fashion and is electrically connected to the connection pads through a plurality of C4 bumps BC (see, e.g., para.0047-0048).
Regarding Claim 9, Tsai (see, e.g., fig. 7, para.0057), in view of Yu and further in view of Hu, shows the coreless substrate package according to claim 7,
wherein BGA balls BS (see, e.g., para.0057) are disposed on the BGA ball pads, respectively.
Claims 5 & 6 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230005808) in view of Yu (US 20210327866) & Hu (US 9543249) and further in view of Kao (US 20230260886).
Regarding Claim 5, Tsai, in view of Yu & Hu, show the coreless substrate package according to claim 4,
Tsai, in view of Yu & Hu, however, fails to show
wherein the at least one insulating layer comprises Ajinomoto Build-up Film (ABF), polyimide, or prepreg.
Kao (see, e.g., fig. 2a, para.0029, para.0034), in a similar device to Tsai, in view of Yu & Hu, teaches that Ajinomoto Build-up Film (ABF), polyimide, or prepreg is an obvious and suitable material for insulating layers of a coreless substrate interconnection structure.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the Ajinomoto Build-up Film (ABF), polyimide, or prepreg of Kao in the device of Tsai, in view of Yu & Hu, as an obvious and suitable material for insulating layers of a coreless substrate interconnection structure.
Regarding Claim 6, Tsai, in view of Yu & Hu, shows the coreless substrate package according to claim 4,
Tsai, in view of Yu & Hu, however, fails to show
wherein the conductive layers comprise copper.
Kao (see, e.g., fig. 2a, para.0029), in a similar device to Tsai, in view of Yu & Hu, teaches that copper is an obvious and suitable material for conductive layers of a coreless substrate interconnection structure.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the copper of Kao in the device of Tsai, in view of Yu & Hu, as an obvious and suitable material for conductive layers of a coreless substrate interconnection structure.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230005808) in view of Yu (US 20210327866) and further in view of Chang (EP 3671831).
Regarding Claim 15, Tsai, in view of Yu, shows the coreless substrate package according to claim 1,
wherein the gap fill material 200 has a top surface that is flush with a top surface of the encapsulant 102, and the passive rear surface 101a-bs of the function silicon die (see, e.g., para.0050).
Tsai, in view of Yu, however, fails to show
wherein the gap fill material has a top surface that is flush with a top surface of the stiffener ring
Chang (see, e.g., fig. 6, para.0060), in a similar device to Tsai, in view of Yu, teaches a configuration wherein a top surface of a gap fill material 150 is flush with a top surface of a stiffener ring and with a top surface of a die would be an obvious and suitable design choice for the level of top surfaces.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Chang in the device of Tsai, in view of Yu, as an obvious and suitable design choice for the level of top surfaces.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814