DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 6-12 are rejected under 35 U.S.C. 103 as being unpatentable over Salama et al. (US 20050017300 A1) herein after “Salama” in view of Cai (US 20080128744 A1).
Regarding claim 1, Fig. 7 of Salama discloses a semiconductor device (Fig. 7, SJR-LDMOST 70, ¶ [0028]) comprising:
a semiconductor layer (see Annotation 1, Fig. 7 of Salama, L1) having a surface (see Annotation 1, Fig. 7 of Salama, TS);
a first region (Fig. 7, n.sup.+ source region 43, ¶ [0028]) and a second region (Fig. 7, n.sup.+ drain region 37, ¶ [0028]) of a first conductivity type (n-type), which are spaced apart from each other in a first direction (x-direction) at the surface (TS) and extend in a second direction (y-direction) orthogonal to the first direction (x-direction), when viewed from a thickness direction (z-direction) orthogonal to the surface (TS);
a channel region (Fig. 7, “an inversion layer forms a channel at the surface of the p-well region 38”, ¶ [0028]) of a second conductivity type (p-type), which is formed between the first region (43) and the second region (37) at the surface (TS) and is adjacent to the first region (43);
a gate electrode (Fig. 7, gate electrode 41, ¶ [0028]) arranged over the channel region (38) via a gate insulating film (Fig. 7, thin oxide layer 39, ¶ [0028]);
a plurality of drift regions (Fig. 7, n-pillars 34, ¶ [0029]) of the first conductivity type (n-type) and a plurality of column regions (Fig. 7, p-pillars 35, ¶ [0029]) of the second conductivity type (p-type), which are arranged between the channel region (38) and the second region (37) and are alternately arranged in the second direction (y-direction);
a buffer region (Fig. 7, n.sup.- epitaxial layer 72, ¶ [0028]) of the first conductivity type (n-type), which is provided between the second region (37) and both the drift regions (34) and the column regions (35).
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Annotation 1, Fig. 7 of Salama
Salama fails to disclose at least one collector region of the second conductivity type, which is provided in the second region.
In the similar field of endeavor of bipolar transistors, Fig. 5B of Cai discloses at least one collector region (Fig. 5B, p+ anode segments 68, ¶ [0058]) of the second conductivity type (p-type), which is provided in the second region (Fig. 5B, “interleaved n+ anode segments 66 and p+ anode segments 68”, ¶ [0058]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the second region of Salama with the collector regions as disclosed by Cai, to allow for faster switching and a higher breakdown voltage (see Cai, ¶ [0059]).
Regarding claim 2, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, but Salama fails to disclose wherein the at least one collector region includes a plurality of collector regions, and the plurality of collector regions are spaced apart from each other in the second direction.
In the similar field of endeavor of bipolar transistors, Fig. 5B of Cai discloses wherein the at least one collector region (68) includes a plurality of collector regions (68), and the plurality of collector regions (68) are spaced apart from each other in the second direction (Fig. 5B, “interleaved n+ anode segments 66 and p+ anode segments 68”, ¶ [0058]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the second region of Salama with the collector regions as disclosed by Cai, to allow for faster switching and a higher breakdown voltage (see Cai, ¶ [0059]).
Regarding claim 3, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, but Salama fails to disclose wherein in the second region, an occupancy rate of the collector region, which is a ratio of a total length of the at least one collector region in the second direction to a range in which the drift regions and the column regions are arranged in the second direction, is greater than or equal to 20% and smaller than or equal to 90%.
In the similar field of endeavor of bipolar transistors, Fig. 5B of Cai discloses wherein in the second region (66), an occupancy rate of the collector region (68), which is a ratio of a total length of the at least one collector region (68) in the second direction to a range in which the drift regions (50) and the column regions (48) are arranged in the second direction, is greater than or equal to 20% and smaller than or equal to 90% (Fig. 5B, “The anode design of FIG. 5B has n+ and p+ regions 66 and 68, respectively, of equal cross sectional area”, therefore the total length of the at least one collector region 68 is 50% of the range in which the drift regions and the column regions are arranged in the second direction).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the second region of Salama with the collector regions as disclosed by Cai, to allow for faster switching and a higher breakdown voltage (see Cai, ¶ [0059]).
Regarding claim 4, Salama and Cai together disclose the semiconductor device of claim 3 as applied above, but Salama fails to disclose wherein the occupancy rate is greater than or equal to 50% and smaller than or equal to 80%.
In the similar field of endeavor of bipolar transistors, Fig. 5B of Cai discloses wherein the occupancy rate is greater than or equal to 50% and smaller than or equal to 80% (Fig. 5B, “The anode design of FIG. 5B has n+ and p+ regions 66 and 68, respectively, of equal cross sectional area”, therefore the total length of the at least one collector region 68 is 50% of the range in which the drift regions and the column regions are arranged in the second direction).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the second region of Salama with the collector regions as disclosed by Cai, to allow for faster switching and a higher breakdown voltage (see Cai, ¶ [0059]).
Regarding claim 6, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, but Salama fails to disclose wherein the collector region and the second region are arranged such that the buffer region is interposed between the semiconductor layer and both the collector region and the second region, in the thickness direction, and
wherein the collector region extends from the surface of the semiconductor layer to the buffer region in the thickness direction.
In the similar field of endeavor of bipolar transistors, Figs. 1A and 5B of Cai disclose wherein the collector region (68) and the second region (66) are arranged such that the buffer region (Fig. 5B, n- well region 42¸¶ [0058]) is interposed between the semiconductor layer (Fig. 1A, buried n well region 16, n- epi region 18, ¶ [0050]) and both the collector region (68) and the second region (66), in the thickness direction, and
wherein the collector region (68) extends from the surface (top surface of 18 in Fig. 1A) of the semiconductor layer (16, 18) to the buffer region (42) in the thickness direction.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the second region of Salama with the buffer region as disclosed by Cai, to increase the breakdown voltage (see Cai, ¶ [0063]).
Regarding claim 7, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, and Salama discloses optimizing the dimensions of the buffer layer (see ¶ [0032]). Salama and Cai fail to explicitly disclose a width of the buffer region in the first direction is longer than or equal to 5 μm and shorter than or equal to 30 μm.
However, it would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the width of the buffer layer of Salama through optimization as disclosed by Salama such that the width of the buffer region in the first direction is longer than or equal to 5 μm and shorter than or equal to 30 μm, to obtain the desired electric field distribution (see Salama, ¶ [0032]) and/or because it has been ruled that changes of dimension are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(1V)(A)).
Regarding claim 8, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, and Salama discloses optimizing the dimensions of the buffer layer (see ¶ [0032]). Salama and Cai fail to explicitly disclose wherein a thickness of the buffer region in the thickness direction is equal to a width of the buffer region in the first direction.
However, it would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the thickness of the buffer layer of Salama through optimization as disclosed by Salama such that the thickness of the buffer region in the thickness direction is equal to a width of the buffer region in the first direction, to obtain the desired electric field distribution (see Salama, ¶ [0032]) and/or because it has been ruled that changes of dimension are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(1V)(A)).
Regarding claim 9, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, but Salama fails to disclose wherein the collector region is arranged at a position overlapping with at least one of the plurality of column regions when viewed from the first direction.
In the similar field of endeavor of bipolar transistors, Figs. 4 and 5B of Cai disclose wherein the collector region (68) is arranged at a position overlapping with at least one of the plurality of column regions (48) when viewed from the first direction.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the second region of Salama with the collector regions as disclosed by Cai, to allow for faster switching and a higher breakdown voltage (see Cai, ¶ [0059]).
Regarding claim 10, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, but Salama fails to disclose wherein the collector region is arranged between two adjacent column regions in the second direction.
In the similar field of endeavor of bipolar transistors, Figs. 4 and 5B of Cai disclose wherein the collector region (68) is arranged between two adjacent column regions (48) in the second direction.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the second region of Salama with the collector regions as disclosed by Cai, to allow for faster switching and a higher breakdown voltage (see Cai, ¶ [0059]).
Regarding claim 11, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, and Fig. 1A of Salama further discloses comprising:
a semiconductor substrate (Fig. 7, substrate 36, ¶ [0028]).
Salama fails to disclose an insulating layer provided over the semiconductor substrate,
wherein the semiconductor layer is provided over the insulating layer.
In the similar field of endeavor of bipolar transistors, Fig. 1A of Cai discloses an insulating layer (Fig. 1A, oxide layer 14, ¶ [0050]) provided over the semiconductor substrate (12),
wherein the semiconductor layer (16, 18) is provided over the insulating layer (14).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the device of Salama with the insulating layer as disclosed by Cai, to isolate the layers (see Cai, ¶ [0060]).
Regarding claim 12, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, and Fig. 1A of Salama further discloses comprising:
a semiconductor substrate (36),
wherein the semiconductor layer (L1) is in contact with an upper surface (TS) of the semiconductor substrate (36).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Salama (US 20050017300 A1) and Cai (US 20080128744 A1) in further view of Kaneko et al. (US 20070090482 A1) herein after “Kaneko”.
Regarding claim 5, Salama and Cai together disclose the semiconductor device of claim 1 as applied above, and Salama discloses optimizing the arrangement interval of the column regions (see ¶ [0031]).
In the similar field of endeavor semiconductor switching devices, Fig. 16 of Kaneko discloses optimizing the arrangement interval of the collector regions (see ¶ [0148]).
Salama, Cai and Kaneko fail to explicitly disclose wherein an arrangement interval of the plurality of collector regions in the second direction is smaller than an arrangement interval of the plurality of column regions in the second direction.
However, it would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the arrangement intervals of Salama through optimization as disclosed by Salama and Kaneko such that the arrangement interval of the plurality of collector regions in the second direction is smaller than an arrangement interval of the plurality of column regions in the second direction, to obtain the desired electric field distribution and on-state resistance (see Salama, ¶ [0032], see Kaneko, ¶ [0149]) and/or because it has been ruled that changes of dimension are prima facie obvious absent persuasive evidence that the particular size is significant (MPEP 2144.04(1V)(A)).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893