Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Claims 15-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/08/2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1, 2, 5, and 7-11 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by United States Patent Application Publication by Hong et al. ( US 20220302172 A1 ). Regarding claim 1 , Hong discloses a semiconductor structure (10) comprising: a first group of field-effect-transistors (FETs) (LNT – lower nanosheet transistor – Para. 38) ; a second group of FETs (UNT – upper nanosheet transistor – Para. 38 ) on top of the first group of FETs; and a half-single-diffusion-break (H-SDB) (400L in Fig. 4B – Hong calls 400L a double diffusion break, instant application used the terminology “Half-single-diffusion-break” or H-SDB. Examiner notes that H-SDB isn’t a known term in the art and that the same structure in Hong for 400L can read on the H-SDB) directly underneath one of the FETs of the second group and being separated from the one of the FETs of the second group by a middle- dielectric-insulator (MDI) layer (132) (Fig. 4B, Where H-SDB 400L is under a 2 nd group FET under UNT-A and there being a MDI layer 132 between the 2nd group FET and the H-SDB 400L) , wherein the H-SDB insulates a source/drain (S/D) region of a first FET of the first group of FETs from a S/D region of a second FET of the first group of FETs (Fig. 4B, 400L separates the S/D region of a FET 100 in LNT and another FET 200 also in the LNT) . Regarding claim 2 , Hong discloses the semiconductor structure of claim 1, wherein the H-SDB is a first H-SDB, further comprising: a second H-SDB (400U) directly on top of one of the FETs of the first group and being separated from the one of the FETs of the first group by the MDI layer (The second H-SDB 400U, while not vertically separated by a MDI layer, is horizontally separated by a MDI layer over to the adjacent FET stacks) , wherein the second H-SDB insulates a S/D region of a first FET of the second group of FETs from a S/D region of a second FET of the second group of FETs (Fig. 4B, 400U separates the S/D region of a FET 100 in UNT and another FET 200 also in the UNT) . Regarding claim 5 , Hong discloses the semiconductor structure of claim 4, and further wherein the one of the FETs of the second group is a nanosheet transistor and the H-SDB is directly underneath a metal gate of the nanosheet transistor, the metal gate of the nanosheet transistor surrounding a set of nanosheets (Hong discloses that the FET structures, including those in Fig. 4B [0017] are nanosheet transistors. Therefore, the FETs of the second group are nanosheet transistors) . Regarding claim 7 , Hong discloses the semiconductor structure of claim 6, and further wherein the one of the FETs of the first group is a nanosheet transistor and the second H-SDB is directly on top of a metal gate of the nanosheet transistor, the metal gate of the nanosheet transistor surrounding a set of nanosheets (Hong discloses that the FET structures, including those in Fig. 4B [0017] are nanosheet transistors. Therefore, the FETs of the second group are nanosheet transistors) . Regarding claim 8 , Hong discloses a semiconductor structure (10) comprising: a first group of field-effect-transistors (FETs) (LNT – lower nanosheet transistor – Para. 38); a second group of FETs (UNT – upper nanosheet transistor – Para. 38) on top of the first group of FETs; and a half-single-diffusion-break (H-SDB) (600U in Fig. 6B – Hong calls 600U a double diffusion break, instant application used the terminology “Half-single-diffusion-break” or H-SDB. Examiner notes that H-SDB isn’t a known term in the art and that the same structure in Hong for 600U can read on the H-SDB) on top of one of the FETs of the first group and being separated from the one of the FETs of the first group by a middle-dielectric-insulator (MDI) layer (132) (Fig. 6B, Where H-SDB 600U is over a 1 st group FET above LNT in the UNT and there being a MDI layer 132 between the 1st group FET and the H-SDB 600U), wherein the H-SDB insulates a source/drain (S/D) region of a first FET of the second group of FETs from a S/D region of a second FET of the second group of FETs (Fig. 6B, 600U separates the S/D region of a FET 100 in UNT and another FET 200 also in the UNT). Regarding claim 9 , Hong discloses the semiconductor structure of claim 8, and further wherein the H-SDB is a first H-SDB, further comprising: a second H-SDB (600L) underneath one of the FETs of the second group and being separated from the one of the FETs of the second group by the MDI layer (The second H-SDB 600L, while not vertically separated by a MDI layer, is horizontally separated by an MDI layer over to the adjacent FET stacks) , wherein the second H-SDB insulates a source/drain (S/D) region of a first FET of the first group of FETs from a S/D region of a second FET of the first group of FETs (Fig. 6B, 600L separates the S/D region of a FET 100 in LNT and another FET 200 also in the LNT). Regarding claim 10 , Hong discloses the semiconductor structure of claim 9, wherein the one of the FETs of the second group is a nanosheet transistor and the second H-SDB is directly underneath a set of nanosheets of the nanosheet transistor (Hong discloses that the FET structures, including those in Fig. 6B [0019] are nanosheet transistors. Therefore, the FETs of the second group are nanosheet transistors) . Regarding claim 11 , Hong discloses the semiconductor structure of claim 10, wherein the first FET of the first group of FETs is a p-type FET and the second FET of the first group of FETs is an n-type FET (Para. 41, “ each of the lower nanosheet transistors LNT may be one of a p-type transistor and an n-type transistor, and each of the upper nanosheet transistor UNT may be the other of the p-type transistor and the n-type transistor ”). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim s 4 and 6 rejected under 35 U.S.C. 103 as being unpatentable as obvious by Hong in view of United States Patent Application Publication by Park et al. ( US 20230343825 A1 ). Regarding claim 4 , Hong discloses the semiconductor structure of claim 1, however, Hong fails to explicitly disclose the polarity of adjacent Source Drain regions where the H-SDB is between wherein the first and the second FET of the first group of FETs have opposite polarities. In a similar field of endeavor, Park discloses a 3D stacked nanosheet device (Para. 3) with diffusions breaks between adjacent gate stacks (Para. 60-63) and there being opposite polarities between the active region of adjacent gate stacks (Claim 3). It is well known in the art that source/drain regions opposite of a diffusion break typically have opposite polarities. This is because the doping arrangements in result in diodes that permit current flow in opposite directions depending on the type of semiconductor (N-type or P-Type), which can lead to the source drain regions connected to different voltages and that can lead to different current flow characteristics. In view of the disclosure of Park , it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Park to Hong at the time the instant application was filed to incorporate polarity of adjacent Source Drain regions where the H-SDB is between wherein the first and the second FET of the first group of FETs have opposite polarities . Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that having a Opposite polarity between adjacent gate stacks across a diffusion break would have in order to allow for different current flow between active regions (Park: Para. 42). Regarding claim 6 , Hong discloses the semiconductor structure of claim 2, however, Hong fails to explicitly disclose wherein the first and the second FET of the second group of FETs have opposite polarities. In a similar field of endeavor, Park discloses a 3D stacked nanosheet device (Para. 3) with diffusions breaks between adjacent gate stacks (Para. 60-63) and there being opposite polarities between the active region of adjacent gate stacks (Claim 3). It is well known in the art that source/drain regions opposite of a diffusion break typically have opposite polarities. This is because the doping arrangements in result in diodes that permit current flow in opposite directions depending on the type of semiconductor (N-type or P-Type), which can lead to the source drain regions connected to different voltages and that can lead to different current flow characteristics. In view of the disclosure of Park , it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Park to Hong at the time the instant application was filed to incorporate polarity of adjacent Source Drain regions where the H-SDB is between wherein the first and the second FET of the second group of FETs have opposite polarities . Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that having a Opposite polarity between adjacent gate stacks across a diffusion break would have in order to allow for different current flow between active regions (Park: Para. 42). Allowable Subject Matter Claims 3, and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: While Diffusion-Break structures are not uncommon in the art, they are not as prevalent in the stacked FET and/or Stacked Nanosheet structures that is seen here. And even less common where in the vertical, there is a FET structure either directly over or directly under a Diffusion Break structure. And even less, where there are multiple types of Diffusion Break all within the same proximate area and structure. Claims 3 and 12-14 all require the stacked FET structure, with at least a Diffusion Break directly under or over a FET from the other group, AND another one in the opposite group doing the same, AND another Diffusion Break through both groups, meaning they require 3 different positions/structure of the Diffusion Break structures. Examiner did not see this in the prior art as either anticipated or in an obvious combination and for these reasons it is believed that at least these claims are found to contain allowable subject matter. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT DANIEL J HIBBERT whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (703)756-1562 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday 8am-5pm EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL J HIBBERT/ Examiner, Art Unit 2899 /ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899