Attorney Docket Number: 5649.5361
Filing Date: 11/06/2023
Claimed Foreign Priority Date: 10/05/2020 (KR10-2020-0127856)
Inventors: Lee et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the application filed 11/06/2023 and preliminary amendment filed 1/19/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA . In the event the determination of the status of the
application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis
(i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of
rejection if the prior art relied upon, and the rationale supporting the rejection, would be the
same under either status.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5-7, 10-12, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 20180301564 A1) in view of Siew (US 20180096934 A1).
Regarding claim 2, Kwon (see, e.g., fig. 2A) shows most aspects of the instant invention including a semiconductor device comprising:
An active pattern (e.g., active pattern AP + semiconductor patterns 122) comprising a lower pattern (e.g., active pattern AP) and sheet patterns (e.g., semiconductor patterns 122 + paragraph 31 “…semiconductor patterns 122 may be embodied in a rectangular parallelepiped nano-sheet shape”);
First and second source/drain patterns (e.g., left-side and center source/drain regions SD respectively) connected to the sheet patterns (e.g., semiconductor patterns 122 + paragraph 31 “…semiconductor patterns 122 may be embodied in a rectangular parallelepiped nano-sheet shape”) to be spaced apart from each other;
A gate structure (e.g., gate structure GS) on the lower pattern (e.g., active pattern AP) comprising a gate electrode (e.g., gate electrode GE);
Kwon (see, e.g., fig. 2A), however, fails to show a first source/drain contact on the first source/drain pattern and comprising a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, while it also fails to show a second source/drain contact on the second source/drain pattern wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, relative to the top surface of the active pattern as a base reference level, and wherein a height from the top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film, and the first source/drain filling film does not contact the top surface of the first source/drain barrier film.
Siew (see, e.g., fig. 2B), in a similar device to Kwon, teaches a first source/drain contact (e.g., left-side contact plug 180A + paragraphs 38-40) on a first source/drain pattern (e.g., left-side source/drain region 110) and comprising a first source/drain barrier film (e.g., conductive barrier layer 184) and a first source/drain filling film (e.g., conductive materials 186) on the first source/drain barrier film (e.g., conductive barrier layer 184), a second source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40) on a second source/drain pattern (e.g., right-side source/drain region 110), and the first source/drain filling film (e.g., conductive materials 186) does not contact the top surface of the first source/drain barrier film (e.g., conductive barrier layer 184).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the contact configuration comprising the barrier and filling film of Siew onto the source/drain pattern of Kwon, in order to facilitate current flow from the source/drain to other regions as necessary, while also including the barrier layer to prevent diffusion into local areas, increasing the integrity and performance within the device. Note that the barrier film is below the filling film, so the distance between the active pattern top surface and the barrier film’s top surface would be less than the distance between the active pattern’s top surface and the filling film’s top surface. In addition, it would have been obvious to one of ordinary skill in the art to limit the barrier layer and filling film height within the interlayer dielectric layer, in order to achieve the expected result of reducing the cost during manufacturing the film within the device. Note that the gate structure of Kwon extends to the top of the interlayer dielectric, so limiting the height of the filling film to extend only partially through the interlayer would result in the gate structure’s top surface being disposed at a higher height.
Regarding claim 3, Kwon (see, e.g., fig. 2A) in view of Siew teaches an interlayer insulating film (e.g., interlayer dielectric layer 150) on the top surface of the first source/drain contact (e.g., contact plug 180A of Siew) wherein a top surface of the interlayer insulating film (e.g., interlayer dielectric layer 150) is substantially coplanar with the top surface of the gate structure (e.g., gate structure GS).
Regarding claim 5, Kwon (see, e.g., fig. 2A) in view of Siew teaches wherein a top surface of the first source/drain filling film (e.g., left-side conductive layer 186 of Siew) is lower than a top surface of the gate electrode (e.g., gate electrode GE) with respect to the top surface of the active pattern (e.g., active pattern AP + semiconductor patterns 122).
Regarding claim 6, Kwon (see, e.g., fig. 2A) in view of Siew teaches wherein a height from the top surface of the active pattern (e.g., active pattern AP + semiconductor patterns 122) to a top surface of the second source/drain contact (e.g., right-side contact plug 180A of Siew) is equal (e.g., note that right-contact plug 180A of Siew reaches the top surface of the interlayer dielectric layer, which is coplanar with the top surface of the gate structure) to a height from the top surface of the active pattern (e.g., active pattern AP + semiconductor patterns 122) to the top surface of the gate structure (e.g., gate structure GS).
Regarding claim 7, Siew (see, e.g., fig. 2B) teaches wherein the second source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40) comprises a second source/drain barrier film (e.g., right-side conductive barrier 184) and a second source/drain filling film (e.g., right-side conductive layer 186) on the second source/drain barrier film (e.g., right-side conductive barrier 184), and the second source/drain filling film (e.g., right-side conductive layer 186) has an integral structure (see, e.g., continuous structure in fig. 2B).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the second source/drain barrier film and filling film of Siew within the second source/drain contact, in order to prevent metal diffusion into the surrounding regions, ensuring the integrity within the device, while simultaneously providing a flow region above the barrier layer to facilitate current flow from the source/drain to other regions as necessary.
Regarding claim 10, Kwon (see, e.g., fig. 2A) in view of Siew teaches wherein the top surface of the first source/drain barrier film (e.g., left-side conductive barrier 184) is higher (e.g., note that sheet pattern 122 lies within the vertical boundary of the source/drain pattern, and the barrier layer extends past the source/drain pattern) than the top surface of the active pattern (e.g., active pattern AP + semiconductor patterns 122) and lower (e.g., see rejection of claim 2) than a top surface of the gate electrode (e.g., gate electrode GE) relative to the top surface of the active pattern (e.g., active pattern AP + semiconductor patterns 122).
Regarding claim 11, Kwon (see, e.g., fig. 2A) shows most aspects of the instant invention including a semiconductor device comprising:
An active pattern (e.g., active pattern AP + semiconductor patterns 122) comprising a lower pattern (e.g., active pattern AP) and sheet patterns (e.g., semiconductor patterns 122 + paragraph 31 “…semiconductor patterns 122 may be embodied in a rectangular parallelepiped nano-sheet shape”);
First and second source/drain patterns (e.g., left-side and center source/drain regions SD respectively) connected to the sheet patterns (e.g., semiconductor patterns 122 + paragraph 31 “…semiconductor patterns 122 may be embodied in a rectangular parallelepiped nano-sheet shape”) to be spaced apart from each other;
A gate structure (e.g., gate structure GS) on the lower pattern (e.g., active pattern AP) comprising a gate electrode (e.g., gate electrode GE);
Kwon (see, e.g., fig. 2A), however, fails to show a first source/drain contact on the first source/drain pattern and comprising a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, while it also fails to show a second source/drain contact on the second source/drain pattern wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, relative to the top surface of the active pattern as a base reference level, wherein the top surface of the first source/drain filling film is higher than or as same as a top surface of the gate electrode with respect to the top surface of the active pattern, and wherein the top surface of the first source/drain filling film is higher than or as same as a top surface of the gate electrode with respect to the top surface of the active pattern, and wherein a height from the top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film, and the first source/drain filling film does not contact the top surface of the first source/drain barrier film.
Siew (see, e.g., fig. 2B), in a similar device to Kwon, teaches a first source/drain contact (e.g., left-side contact plug 180A + paragraphs 38-40) on a first source/drain pattern (e.g., left-side source/drain region 110) and comprising a first source/drain barrier film (e.g., conductive barrier layer 184) and a first source/drain filling film (e.g., conductive materials 186) on the first source/drain barrier film (e.g., conductive barrier layer 184), a second source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40) on a second source/drain pattern (e.g., right-side source/drain region 110), wherein and the first source/drain filling film (e.g., conductive materials 186) does not contact the top surface of the first source/drain barrier film (e.g., conductive barrier layer 184).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the contact configuration comprising the barrier and filling film of Siew onto the source/drain pattern of Kwon, in order to facilitate current flow from the source/drain to other regions as necessary, while also including the barrier layer to prevent diffusion into local areas, increasing the integrity and performance within the device. Note that the barrier film is below the filling film, so the distance between the active pattern top surface and the barrier film’s top surface would be less than the distance between the active pattern’s top surface and the filling film’s top surface. In addition, the filling film makes contact with the top of the ILD, which is above the gate electrode. In addition, it would have been obvious to one of ordinary skill in the art to limit the barrier height within the interlayer dielectric layer, in order to achieve the expected result of reducing the cost during manufacturing the barrier layer within the device. Note that the gate structure of Kwon extends to the top of the interlayer dielectric, so limiting the height of the barrier film to extend only partially through the interlayer would result in the gate structure’s top surface being disposed at a higher height.
Regarding claim 12, Kwon (see, e.g., fig. 2A) in view of Siew teaches an interlayer insulating film (e.g., interlayer dielectric layer 150) on the top surface of the first source/drain contact (e.g., contact plug 180A of Siew) wherein a top surface of the interlayer insulating film (e.g., interlayer dielectric layer 150) is substantially coplanar with the top surface of the gate structure (e.g., gate structure GS).
Regarding claim 14, Kwon (see, e.g., 2A) in view of Siew teaches the gate structure (e.g., gate structure GS) comprises a gate capping pattern (e.g., gate capping pattern GP) on the gate electrode (e.g., gate electrode GE), and a height from the top surface of the active pattern (e.g., active pattern AP + semiconductor patterns 122) to a top surface of the second source/drain contact (e.g., right-side contact plug 180A) is equal (e.g., note that both extend to the top of the interlayer dielectric) to a height from the top surface of the active pattern (e.g., active pattern AP + semiconductor patterns 122) to a top surface of the gate capping pattern (e.g., gate capping pattern GP).
Regarding claim 15, Siew (see, e.g., fig. 2B) teaches wherein the second source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40) comprises a second source/drain barrier film (e.g., right-side conductive barrier 184) and a second source/drain filling film (e.g., right-side conductive layer 186) on the second source/drain barrier film (e.g., right-side conductive barrier 184), and the second source/drain filling film (e.g., right-side conductive layer 186) has an integral structure (see, e.g., continuous structure in fig. 2B).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the second source/drain barrier film and filling film of Siew within the second source/drain contact, in order to prevent metal diffusion into the surrounding regions, ensuring the integrity within the device, while simultaneously providing a flow region above the barrier layer to facilitate current flow from the source/drain to other regions as necessary.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Siew further in view of Bi (US 20180096990 A1).
Regarding claim 4, Kwon in view of Siew fails to teach airgaps between the first source/drain filling film and the gate structure.
Bi (see, e.g., 8B), in a similar device to Kwon in view of Siew teaches airgaps (e.g., airgaps 804 and 806) between a source/drain contact (e.g., source contact 302 + drain contact 304) and a gate structure (e.g., conductive gate 120).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the airgaps of Bi within the ILD and between the filling film/contact and gate structure of Kwon in view of Siew, in order to reduce the parasitic capacitance/electrical leakage within the device.
Regarding claim 13, Kwon in view of Siew fails to teach airgaps between the first source/drain filling film and the gate structure.
Bi (see, e.g., 8B), in a similar device to Kwon in view of Siew teaches airgaps (e.g., airgaps 804 and 806) between a source/drain contact (e.g., source contact 302 + drain contact 304) and a gate structure (e.g., conductive gate 120).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the airgaps of Bi within the ILD and between the filling film/contact and gate structure of Kwon in view of Siew, in order to reduce the parasitic capacitance/electrical leakage within the device.
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Siew further in view of Mannebach (US 20200411651 A1).
Regarding claim 9, Kwon (see, e.g., fig. 2A) shows the first source/drain pattern (e.g., left-side source/drain regions SD) is spaced apart from the second source/drain pattern (e.g., center source/drain regions SD) in a first direction.
Kwon (see, e.g., fig. 2A), however, fails to teach the first source/drain filling film comprises a lower portion including the first source/drain barrier film thereon and an upper portion on the lower portion, wherein a width of the upper portion of the first source/drain filling film in the first direction decreases in a direction away from the first source/drain pattern.
Siew (see, e.g., fig. 2B) teaches the first source/drain filling film (e.g., left-side conductive layer 186) comprises a lower portion (e.g., bottom portion of 186 associated with barrier film 184) including the first source/drain barrier film (e.g., left-side conductive barrier 184) thereon and an upper portion (e.g., upper portion on bottom portion) on the lower portion (e.g., bottom portion of 186 associated with barrier film 184).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the upper and lower portion of the filling film of Siew within the filling film of Kwon in view of Siew, in order to achieve the expected result of providing additional flow area within the film to facilitate current flow as necessary.
Kwon in view of Siew, however, fails to teach a width of the upper portion of the first source/drain filling film in the first direction decreases in a direction away from the first source/drain pattern.
Mannebach (see, e.g., fig. 2D), in a similar device to Kwon in view of Siew, teaches a width of the source/drain contact (e.g., conductor contact 259) decreases in a direction away from a source/drain pattern (e.g., source/drain region 253).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the decreasing contact width configuration of Mannebach within the source/drain contact/filling film of Kwon in view of Siew, in order to reduce the contact resistance and improve the performance within the device.
Regarding claim 17, Kwon (see, e.g., fig. 2A) shows the first source/drain pattern (e.g., left-side source/drain regions SD) is spaced apart from the second source/drain pattern (e.g., center source/drain regions SD) in a first direction.
Kwon (see, e.g., fig. 2A), however, fails to teach the first source/drain filling film comprises a lower portion including the first source/drain barrier film thereon and an upper portion on the lower portion, wherein a width of the upper portion of the first source/drain filling film in the first direction decreases in a direction away from the first source/drain pattern.
Siew (see, e.g., fig. 2B) teaches the first source/drain filling film (e.g., left-side conductive layer 186) comprises a lower portion (e.g., bottom portion of 186 associated with barrier film 184) including the first source/drain barrier film (e.g., left-side conductive barrier 184) thereon and an upper portion (e.g., upper portion on bottom portion) on the lower portion (e.g., bottom portion of 186 associated with barrier film 184).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the upper and lower portion of the filling film of Siew within the filling film of Kwon in view of Siew, in order to achieve the expected result of providing additional flow area within the film to facilitate current flow as necessary.
Kwon in view of Siew, however, fails to teach a width of the upper portion of the first source/drain filling film in the first direction decreases in a direction away from the first source/drain pattern.
Mannebach (see, e.g., fig. 2D), in a similar device to Kwon in view of Siew, teaches a width of the source/drain contact (e.g., conductor contact 259) decreases in a direction away from a source/drain pattern (e.g., source/drain region 253).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the decreasing contact width configuration of Mannebach within the source/drain contact/filling film of Kwon in view of Siew, in order to reduce the contact resistance and improve the performance within the device.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Siew further in view of Yang (US 20200152739 A1).
Regarding claim 8, Kwon in view of Siew teaches the second source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40) comprises a lower source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40)), wherein the lower source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40) comprises a lower source/drain barrier film (e.g., right-side conductive barrier 184) and a lower source/drain filling film (e.g., right-side conductive layer 186) on the lower source/drain barrier film (e.g., right-side conductive barrier 184).
Kwon in view of Siew, however, fails to teach the second source/drain contact comprises an upper source/drain contact on the lower source/drain contact.
Yang (see, e.g., fig. 2), in a similar device to Kwon in view of Siew, teaches an upper source/drain contact (e.g., contacts 230) on a lower source/drain contact (e.g., source contact 222).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the upper contacts of Yang on the lower source/drain contact of Kwon in view of Siew, in order to achieve the expected result of extending the conductivity for further current flow and additional electrical coupling as necessary.
Regarding claim 16, Kwon in view of Siew teaches the second source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40) comprises a lower source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40)), wherein the lower source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40) comprises a lower source/drain barrier film (e.g., right-side conductive barrier 184) and a lower source/drain filling film (e.g., right-side conductive layer 186) on the lower source/drain barrier film (e.g., right-side conductive barrier 184).
Kwon in view of Siew, however, fails to teach the second source/drain contact comprises an upper source/drain contact on the lower source/drain contact.
Yang (see, e.g., fig. 2), in a similar device to Kwon in view of Siew, teaches an upper source/drain contact (e.g., contacts 230) on a lower source/drain contact (e.g., source contact 222).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the upper contacts of Yang on the lower source/drain contact of Kwon in view of Siew, in order to achieve the expected result of extending the conductivity for further current flow and additional electrical coupling as necessary.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Siew further in view of Li (CN 110350027 A).
Regarding claim 18, Kwon (see, e.g., fig. 2A) shows most aspects of the instant invention including a semiconductor device comprising:
A fin-type pattern (e.g., active pattern AP + paragraph 29 “The active patterns AP may have a fin shape…”) extending in a first direction (see, e.g., paragraph 29 “…fin shape protruding in a third direction D3 perpendicular to a top surface of the substrate 100”);
First and second source/drain patterns (e.g., left-side and center source/drain regions SD respectively) disposed on the fin-type pattern (e.g., active pattern AP + paragraph 29 “The active patterns AP may have a fin shape…”) to be spaced apart from each other in the first direction to be spaced apart from each other;
A gate structure (e.g., gate structure GS) on the fin-type pattern (e.g., active pattern AP + paragraph 29 “The active patterns AP may have a fin shape…”), and comprising a gate electrode (e.g., gate electrode GE);
Kwon (see, e.g., fig. 2A), however, fails to show a dummy protruding pattern extending in the first direction and spaced apart from the fin-type pattern in a second direction crossing the first direction, a field insulating film covering a portion of a sidewall of the fin-type pattern and a top surface of the dummy protruding pattern, a first source/drain contact on the first source/drain pattern and comprising a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, while it also fails to show a second source/drain contact on the second source/drain pattern wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, relative to the top surface of the fin-type pattern as a base reference level, and wherein a height from the top surface of the fin-type pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the fin-type pattern to a top surface of the first source/drain filling film, and the first source/drain filling film does not contact the top surface of the first source/drain barrier film.
Siew (see, e.g., fig. 2B), in a similar device to Kwon, teaches a first source/drain contact (e.g., left-side contact plug 180A + paragraphs 38-40) on a first source/drain pattern (e.g., left-side source/drain region 110) and comprising a first source/drain barrier film (e.g., conductive barrier layer 184) and a first source/drain filling film (e.g., conductive materials 186) on the first source/drain barrier film (e.g., conductive barrier layer 184), a second source/drain contact (e.g., right-side contact plug 180A + paragraphs 38-40) on a second source/drain pattern (e.g., right-side source/drain region 110), and the first source/drain filling film (e.g., conductive materials 186) does not contact the top surface of the first source/drain barrier film (e.g., conductive barrier layer 184).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the contact configuration comprising the barrier and filling film of Siew onto the source/drain pattern of Kwon, in order to facilitate current flow from the source/drain to other regions as necessary, while also including the barrier layer to prevent diffusion into local areas, increasing the integrity and performance within the device. Note that the barrier film is below the filling film, so the distance between the fin-type pattern top surface and the barrier film’s top surface would be less than the distance between the fin-type pattern’s top surface and the filling film’s top surface. In addition, it would have been obvious to one of ordinary skill in the art to limit the barrier layer height within the interlayer dielectric layer, in order to achieve the expected result of reducing the cost during manufacturing the film within the device. Note that the gate structure of Kwon extends to the top of the interlayer dielectric, so limiting the height of the barrier layer to extend only partially through the interlayer dielectric would result in the gate structure’s top surface being disposed at a higher height than one of the top surfaces of the source/drain contact.
Kwon in view of Siew, however, fails to teach a dummy protruding pattern extending in the first direction and spaced apart from the fin-type pattern in a second direction crossing the first direction and a field insulating film covering a portion of a sidewall of the fin-type pattern and a top surface of the dummy protruding pattern.
Li (see, e.g., fig. 2B), in a similar device to Kwon in view of Siew, teaches a dummy protruding pattern (e.g., dummy fin-type pattern DF) extending in a first direction (e.g., vertical direction) and spaced apart from fin-type patterns (e.g., fin type patterns F1 + F2) in a second direction (e.g., horizontal direction) crossing the first direction (e.g., vertical direction) and a field insulating film (e.g., field insulating film 110 + insulating liner 150) covering a portion of a sidewall of the fin type pattern (e.g., fin type patterns F1 + F2) and a top surface of the dummy protruding pattern (e.g., dummy fin-type pattern DF).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dummy protruding pattern and the field insulating film configuration of Li within the device of Kwon in view of Siew, in order to provide increased pattern density and uniformity, in addition to the insulation layer to protection/prevention for potential electrical shortages or leakage currents within the device. Note that the gate structure of Kwon in view of Siew is disposed above the placement area of the field insulating film.
Regarding claim 19, Kwon (see, e.g., fig. 2A) in view of Siew further in view of Li fails to explicitly teach wherein a top surface of the first source/drain filling film is lower than a top surface of the gate electrode with respect to the top surface of the fin-type pattern.
However, it would have been obvious to one of ordinary skill in the art at the time of filing the
invention to modify the size of the filling film and the distance it expands into the interlayer dielectric, as reducing the length of the film to reside lower than the adjacent gate electrode would save manufacturing costs due to less used material while forming the device. Furthermore, it has been held that a mere change in size of an element is generally recognized as being within the level of ordinary skill in the art. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04(IV)(A). One having ordinary skill in the art would have had success in making this modification because Wu further teaches that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or process for carrying out the same purposes of the present disclosure (see paragraph 116 of Siew).
Regarding claim 20, Kwon (see, e.g., fig. 2A) in view of Siew teaches wherein the top surface of the first source/drain filling film (e.g., left-side conductive layer 186) is higher than (e.g., note that conductive layer 186 expands to the top surface of the interlayer dielectric) as a top surface of the gate electrode (e.g., gate electrode GE) with respect to the top surface of the fin type pattern (e.g., active pattern AP + paragraph 29 “The active patterns AP may have a fin shape…”).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Siew further in view of Li and Mannebach.
Regarding claim 21, Siew (see, e.g., fig. 2B) teaches the first source/drain filling film (e.g., left-side conductive layer 186) comprises a lower portion (e.g., bottom portion of 186 associated with barrier film 184) including the first source/drain barrier film (e.g., left-side conductive barrier 184) thereon and an upper portion (e.g., upper portion on bottom portion) on the lower portion (e.g., bottom portion of 186 associated with barrier film 184).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the upper and lower portion of the filling film of Siew within the filling film of Kwon in view of Siew further in view of Li, in order to achieve the expected result of providing additional flow area within the film to facilitate current flow as necessary.
Kwon in view of Siew further in view of Li, however, fails to teach a width of the upper portion of the first source/drain filling film in the first direction decreases in a direction away from the first source/drain pattern.
Mannebach (see, e.g., fig. 2D), in a similar device to Kwon in view of Siew further in view of Li, teaches a width of the source/drain contact (e.g., conductor contact 259) decreases in a direction away from a source/drain pattern (e.g., source/drain region 253).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the decreasing contact width configuration of Mannebach within the source/drain contact/filling film of Kwon in view of Siew further in view of Li, in order to reduce the contact resistance and improve the performance within the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814