DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No.11,881,464. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reasoning:
Current Application 18/502,334
US Patent 11,881,464
Claim 1: 0. A power amplifier device package, comprising:
1.a substrate; and
2.a first transistor die comprising a bottom surface on the substrate and top gate and
drain contacts on a top surface of the first die opposite the bottom surface,
3.wherein at least one of the top gate contact or the top drain contact is electrically connected to a respective bottom gate or drain contact on the bottom surface by a respective conductive via structure, and
4.wherein the top gate contact or the top drain contact is connected to a first circuit
configured to provide a first function at the top surface of the first die, and
5.wherein the respective bottom gate or drain contact is connected to a second circuit configured to provide a second function at the bottom surface of the first die.
Claim 1. 0.A radio frequency (RF) power amplifier device package, comprising:
1.a substrate;
2.a first die, comprising a plurality of transistor cells, attached to the substrate at a bottom surface of the first die and comprising top gate or drain contacts on a top surface of the first die opposite the bottom surface,
3.wherein the top and bottom surfaces are external surfaces of the first die, and at least one of the top gate or drain contacts is electrically connected to at least one respective bottom gate or drain contact on the bottom surface of the first die by at least one respective conductive via structure that extends therebetween; and
4.an integrated interconnect structure on the first die opposite the substrate, the integrated interconnect structure comprising a first contact pad on the top gate contact or the top drain contact of the first die, and
5.at least one second contact pad connected to a package lead, a contact of a second die, impedance matching circuitry, and/or harmonic termination circuitry.
Claims 1 of the current application and the US patent have been sectioned per limitations. It is evident that the preamble 0., and limitations 1-3 of the current claim 1 are anticipated by the corresponding limitations of claim 1 of the US patent. Limitations 4 and 5 of claim 1 of the current application refers to first and second circuits, which are broader that interconnect structure mentioned in the corresponding sections (4, 5) of the US patent and hence these limitations of the current claim are anticipated by the corresponding interconnect structures of claim 1 of the US patent. Thus claim 1 of the current application is broader form of claim 1 of US patent and constitutes obviousness double patenting rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, and 10-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jones (US 2016/0285420, cited by the applicant).
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Fig. 15 of Jones annotated by the examiner for ease of reference.
Regarding claims 1 and 15, Jones discloses in Figs. 1-16, a power amplifier device package (device 1500, §0072, Fig. 15) comprising:
a substrate (semiconductor substrate 650 having top and bottom semiconductor substrate surfaces 652, 654, Fig. 6, §0047); and
a first transistor die (die 450) comprising a bottom surface (654) on the substrate (650) and top gate (control terminals 422, 423, e.g., gate) and drain (drain terminals 424, 425) contacts on a top surface (652) of the first die opposite the bottom surface (654), wherein at least one of the top gate contact (422, 423) or the top drain contact (424, 425) is electrically connected to a respective bottom gate (input conductive feature 502, 503) or drain (output conductive feature 504, 505) contact on the bottom surface (654) of the first die (450) by a respective conductive via structure (a first set of conductive structures 660 including TSVs 661 for gate, and conductive structures 670 including TSVs 671 for drain, §0056, §0062, Fig. 6); and
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Fig. 6 of Jones annotated by the examiner for ease of reference.
wherein the top gate contact (422, 423) or the top drain contact (424, 425) is connected to a first circuit (input circuit 110 / output circuit 130, Figs. 1, 4, 6) configured to provide a first function (impedance matching / signal filtering at the top surface, §0029, §0031) at the top surface (652) of the first die (450), and wherein the respective bottom gate (502, 503) or drain contact (504, 505) is connected to a second circuit (package leads 1202-1205 / conductive interconnect structures coupled to the lead frame or PCB, §0079, Figs. 12, 15, 16) configured to provide a second function (signal input/output routing at the bottom surface, §0079) at the bottom surface (654) of the first die (450).
Regarding claim 2, Jones further teaches that the top gate contact (461) or the top drain contact (471) is connected to the first circuit (input circuit 110 / output circuit 130) free of wirebonds at the top surface of the first die (die 450 replaces wire bond arrays with integrated spiral inductors 416, 417, 434, 435 and through-substrate vias 661, 671, §0024, §0090), and wherein the respective bottom gate (502) or drain contact (504) is connected to the second circuit (leads 1202-1205) free of wirebonds at the bottom surface of the first die (§0090: "reduction or elimination of inductors implemented using wire bonds").
Regarding claims 3 and 16, Jones teaches the first circuit (input circuit 110 / output circuit 130) comprises an inductance element (integrated spiral inductor 116 / 134 implemented as spiral inductors 416, 417 / 434, 435 in the die's build-up layers 680, §0057, §0063, Fig. 4), and the second circuit comprises a package lead (input leads 1202, 1203 for the gate-side and output leads 1204, 1205 for the drain-side, §0079, Fig. 12).
Regarding claims 4 and 17, Jones teaches the inductance element (spiral inductors 416, 417 / 434, 435) comprises an integrated interconnect structure (build-up layers 680 including portions 480, 482, Fig. 4) having a first contact pad (node 461 coupled to gate contact 422, 423 for input inductors 416, 417; and portions 436, 437 coupled to drain terminals 424, 425 for output inductors 434, 435) on the top gate contact (422, 423) or the top drain contact (424, 425) of the first die (§0057, §0065, Figs. 4, 6).
Regarding claim 5, Jones teaches conductive routing on the substrate (conductive interconnect structures including conductive features 502-506 on the bottom die surface 654, and TSV structures 660, 670 providing continuous electrical paths, §0056, §0062; further, when mounted to PCB 1610, leads 1202-1205 provide routing on the PCB substrate), wherein the respective bottom gate (502) or drain contact (504) is coupled to the package lead (1202, 1204) by the conductive routing (conductive features 502-506 are directly coupled to leads 1202-1205, §0079, Figs. 12-16).
Regarding claims 6 and 19, Jones teaches the top gate contact (422, 423) or the top drain contact (424, 425) having the first contact pad of the integrated interconnect structure thereon is electrically connected to the respective bottom gate (502) or drain contact (504) by the respective conductive via structure (TSVs 661, 671 for input gate and output drain paths respectively, extending between the top semiconductor substrate surface 652 and bottom surface 654, §0056, §0062, Fig. 6).
Regarding claim 7, Jones teaches the integrated interconnect structure is an integrated passive device (IPD) including one or more passive electronic components (integrated spiral inductors 416, 417, 434, 435 and metal-insulator-metal (MIM) capacitors 414, 415, 432, 433, formed from build-up layers 680 over and coupled to the top semiconductor substrate surface 652, §0047, §0057, §0058, §0063, §0066, Figs. 4, 6, 8).
Regarding claim 8, Jones teaches the IPD is configured to provide a shunt inductance (shunt inductive element 134 / inductors 434, 435, having a first terminal coupled to the drain of transistor 120 and a second terminal coupled to the RF cold point node 142 / node 442, forming a shunt path to ground, §0032, §0033, §0065, Fig. 1).
Regarding claim 10, Jones teaches the IPD comprises an insulating material between conductive elements thereof to define at least one capacitor integrated therein (MIM capacitors 414, 415, 432, 433, each including vertically aligned portions of two conductive layers 683, 682 forming first and second capacitor plates 814, 815 / 816, 817 with inter-layer dielectric between the capacitor plates, §0058, §0066, Fig. 8).
Regarding claim 11, Jones teaches transistor cells of the first transistor die (die 450 includes transistors 420, 421 each comprising a plurality of parallel-aligned drain regions 1025 and source regions 1030 forming multiple transistor cells, Fig. 10, §0060) comprise a first stage of a radio frequency (RF) amplifier circuit (main amplifier stage 1820 of Doherty amplifier 1800, §0097, Fig. 18), and further comprising a second transistor die on the substrate and comprising transistor cells that define a second stage of the RF amplifier circuit (transistor 421 of die 450 defines the peaking amplifier stage 1821, with its own transistor cells shown in Figs. 4, 10, §0069, §0097; alternatively, a second die may be separately coupled to the module substrate 2110 as shown in the amplifier system 1900 / amplifier module 2400, Figs. 23-24, §0124).
Regarding claim 12, Jones teaches the first transistor die (450) is attached to the substrate (650) at a source contact (voltage reference terminal 506, the ground-coupled feature on the bottom surface, Figs. 5, 6, §0055) on the bottom surface (654) thereof adjacent the respective bottom gate (502) or drain contact (504) (conductive features 502-506 are arranged on the bottom die surface 654 with voltage reference terminal 506 positioned adjacent to input features 502, 503 and output features 504, 505, Fig. 5).
Regarding claim 13, Jones teaches the respective bottom gate or drain contact includes both a bottom gate contact (input conductive features 502, 503) and a bottom drain contact (output conductive features 504, 505), and wherein the source contact (voltage reference feature 506) is between the bottom gate contact (502, 503) and the bottom drain contact (504, 505) on the bottom surface of the first die (conductor-less regions 584, 586 separate input from ground, and ground from output on the bottom surface 654, Figs. 5, 6, §0053).
Regarding claim 14, Jones teaches the first transistor die (450) comprises a Group III nitride-based material on silicon carbide (SiC) (the semiconductor substrate 650 may comprise GaN on silicon carbide, §0049), and wherein the respective conductive via structure comprises a through silicon carbide (TSiC) via (TSVs 661, 664, 671, 863, 865, 869 extend through the SiC-based substrate 650, §0049, Fig. 6).
Regarding claim 18, Jones teaches the integrated interconnect structure (480, 482, build-up layers 680) is an integrated passive device (IPD) including one or more passive electronic components (spiral inductors 416, 417, 434, 435 and MIM capacitors 414, 415, 432, 433, §0057, §0058, §0063, §0066), wherein the first contact pad (node 461 / portions 436, 437) is electrically connected to the one or more passive electronic components (inductors 416, 417 / 434, 435) and is connected to the top gate contact (422, 423) or the top drain contact (424, 425) by a conductive bump (the TSV and conductive layer interconnections between the passive device and the gate/drain contacts, §0057, §0063, Figs. 4, 6) therebetween.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Brech in view of Szymanowski (US 2021/0194440, effectively filed on Dec. 19, 2019).
Regarding claim 9, Jones discloses the claimed invention as recited in claim 7, and further teaches a first contact pad (node 461 / portions 436, 437) on the integrated passive device coupled to the top gate or drain contact of the first transistor die. Jones also teaches conductive coupling between die components using TSV structures and conductive layer portions (§0056, §0057, §0062, §0063).
However, Jones does not explicitly disclose the first contact pad being a bond pad on a surface of the IPD that is facing the top surface of the first transistor die, wherein the bond pad is connected to the top gate or drain contact by a conductive bump there between.
Szymanowski (US 2021/0194440) discloses an RF power amplifier package wherein an integrated passive device (IPD) is flip-chip mounted onto a transistor die using conductive bumps, with bond pads on the facing surface of the IPD electrically connected to the gate or drain contacts of the transistor die by conductive bumps therebetween (Fig. 5, §0035-0040 of Szymanowski).
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Fig. 5 of Szymanowski annotated by the examiner for ease of reference.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to implement the IPD-to-die connection in Jones using flip-chip bump bonding as taught by Szymanowski, in the same field of RF power amplifier packaging. Such modification provides well-known advantages of reduced parasitic inductance and improved high-frequency performance compared to wire bonding, which is a recognized benefit in the RF power amplifier art.
Because of such modification, the resultant combination also teaches claim 20, wherein the second die is coupled to the top gate or drain contact by the integrated interconnect structure through conductive bumps, as taught by Szymanowski.
Regarding claim 21, Jones discloses the claimed invention as recited in claims 1 and 17 and teaches a first transistor die 450 comprising first and second amplifier paths 400, 401 capable of implementation in a Doherty amplifier topology (§0069, §0091, Figs. 18-19). Jones also teaches inclusion of multiple die on a common module substrate to form a more complex amplifier system (§0104, §0117, Figs. 21-26).
However, Jones does not explicitly teach a second die coupled to the top gate or drain contact by the integrated interconnect structure wherein the second die separately comprises one or more capacitors that define the impedance matching circuitry, or a plurality of transistor cells that define a stage of an RF amplifier circuit.
Szymanowski in Fig. 5 discloses a second die (570) comprising transistor cells (572) that define a second stage of the RF amplifier circuit, and separately teaches the second die comprising one or more capacitors (564, 568) that define at least a portion of the impedance matching circuitry between stages.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to implement the second die configuration of Szymanowski within the Jones amplifier module architecture, in the same field of RF power amplifier packaging. Such a modification constitutes an obvious extension of the Jones amplifier circuit for a higher-power, higher-gain version of an RF power amplifier, as such multi-stage configurations are well known in the art. Accordingly, the resultant combination teaches a second die comprising one or more capacitors or transistor cells that define a stage of an RF amplifier circuit as recited in claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bob Pascal can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Examiner, Art Unit 2843