Prosecution Insights
Last updated: May 29, 2026
Application No. 18/502,440

SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Nov 06, 2023
Priority
May 10, 2021 — JP 2021-079846 +2 more
Examiner
NICELY, JOSEPH C
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Murata Manufacturing Co. Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
606 granted / 784 resolved
+9.3% vs TC avg
Strong +20% interview lift
Without
With
+20.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
828
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
78.5%
+38.5% vs TC avg
§102
8.4%
-31.6% vs TC avg
§112
6.8%
-33.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 784 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I (claims 1, 5-8, and 12) in the reply filed on 3/16/2026 is acknowledged. Claims 2-4, 9-11, and 13-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/16/2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Objections Claim 1 is objected to because of the following informalities: in line 4, "surfaces" should be amended to read -surface-. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 5, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kagawa et al (JP 2020-170782 and Kagawa hereinafter; a machine translation is used as an English language equivalent) in view of . As to claims 1, 5, and 12: Kagawa discloses [claim 1] a semiconductor device (Fig. 25) comprising: a substrate (1; [0026]) having a first principal surface (1a; [0011]) and a second principal surface (bottom surface of 1) opposed to each other in a thickness direction (vertical direction), wherein the first principal surfaces (1a) includes a step (6a and 6b; [0061]) in a plan view from the thickness direction (vertical direction); an insulating film (2; [0026]) on the first principal surface (1a) of the substrate (1); a first electrode layer (21; [0027]) on the insulating film (2) and positioned within a boundary (21 is formed between the step 6a and 6b; claim doesn’t state that the first electrode is formed only within the boundary, just that it is at least within the boundary) defined by the step (6a and 6b) in the plan view; a dielectric film (3; [0028]) on the first electrode layer (21); a second electrode layer (22; [0029]) on the dielectric film (3); a moisture-resistant film (moisture-resistant film made of SiN below 41; [0031]) on the dielectric film (3) and the second electrode layer (22); a protective layer (41; [0031]) on the moisture-resistant film (moisture-resistant film made of SiN below 41); and an outer electrode (62; [0032]) penetrating through the protective layer (41); [claim 5] wherein the insulating film (2), the dielectric film (3), and the moisture-resistant film (moisture-resistant film made of SiN below 41) extend along the step (the three films all extend along a direction of the step comprising 6a and 6b); [claim 12] wherein the outer electrode (62) is a first outer electrode (62) connected to the first electrode layer (21); and the semiconductor device includes a second outer electrode (61; [0032]) penetrating the protecting layer (41) and connected to the second electrode layer (22). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kagawa. As to claims 6 and 7: Although the structure disclosed by Kagawa shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose: [claim 6] wherein a height of the step is 0.1% to 20% of a thickness of a portion of the substrate where the first electrode layer is positioned; [claim 7] wherein a width of the step is 0.1% to 20% of a width of the substrate, and length of the step is 0.1% to 20% of a length of the substrate. Kagawa fails to expressly disclose the dimensions of step 6a and 6b. However, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to form the step 6a and 6b such that the height, width, and length are within the claimed range (relative to the respective substrate dimension) as the length, width, and height are result effective variables as they affect the charge retention capability of the capacitor as the dimensions of the groove change correspond to the side of the capacitor. Allowable Subject Matter Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JOSEPH C. NICELY Primary Examiner Art Unit 2813 /JOSEPH C. NICELY/Primary Examiner, Art Unit 2813 3/31/2026
Read full office action

Prosecution Timeline

Nov 06, 2023
Application Filed
Apr 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12641784
MEMORY DEVICES AND METHODS FOR FORMING THE SAME
3y 4m to grant Granted May 26, 2026
Patent 12622037
GATE CUT SUBSEQUENT TO REPLACEMENT GATE
4y 5m to grant Granted May 05, 2026
Patent 12615830
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
3y 5m to grant Granted Apr 28, 2026
Patent 12610832
PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF
2y 6m to grant Granted Apr 21, 2026
Patent 12588438
LAYER STRUCTURES INCLUDING DIELECTRIC LAYER, METHODS OF MANUFACTURING DIELECTRIC LAYER, ELECTRONIC DEVICE INCLUDING DIELECTRIC LAYER, AND ELECTRONIC APPARATUS INCLUDING ELECTRONIC DEVICE
3y 4m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
97%
With Interview (+20.1%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 784 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month