DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190122820 (Harada et al) in view of US 5622596 (Armacost et al).
Concerning claim 1, Harada discloses a semiconductor device comprising (Fig. 1): a substrate (1); a first electrode layer (3) on the substrate; a dielectric film (4) on the first electrode layer; a second electrode layer (5) on the dielectric film; a protective layer (6) covering the first electrode layer and the second electrode layer (Fig. 1 and [0023]); and an outer electrode (7, which consists of 7a and 7b) penetrating the protective layer, wherein the dielectric film includes silicon nitride ([0029])
Harada does not disclose that an atomic concentration ratio of Si to a total amount of Si and N contained in the dielectric film is 43 atom% to 70 atom%. However, Armacost discloses the manufacture and use of a silicon nitride that has a higher atomic percent of silicon (43.1 to 65 atomic percent) with insulating characteristics (col. 2 lines 52-65) and a shift in capacitance voltage due to charge trapping abilities (col. 3 lines 1-5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the silicon nitride dielectric film of Harada to increase the atomic concentration ratio of Si to the range disclosed by Armacost in order to increase the charge trapping characteristics of the dielectric layer for use in a capacitor device.
Continuing to claim 2, Harada in view of Armacost disclose further comprising an insulating film (Harada 2) between the substrate and the first electrode layer (Fig. 1 and [0023]).
Considering claim 5, Harada in view of Armacost disclose wherein a content of F contained in the dielectric film is 10-9 cm⁻³ or smaller (Harada [0029], note that form examination purposes the examiner is relying on the dielectric film being SiN and there is no mention of F in the film so the examiner is interpreting that the F contained in the film is 0).
Referring to claim 6, Harada in view of Armacost disclose wherein the outer electrode is a first outer electrode (Harada 7b) connected to the first electrode layer, and the semiconductor device further comprises a second outer electrode (Harada 7a) connected to the second electrode layer (Harada Fig. 1).
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190122820 (Harada et al) in view of US 5622596 (Armacost et al) as applied to claim 1 above, and further in view of US 20110193194 (Takahashi et al).
Regarding claims 3 and 4 (with these claims being similar in scope), Harada in view of Armacost disclose forming the semiconductor device.
Harada in view of Armacost does not disclose further comprising a moisture-resistant film on the dielectric film and the second electrode layer, and between the protective layer and the first electrode layer and the second electrode layer. However, Takahashi discloses an analogous semiconductor structure (thin film capacitor) with a configuration in which a moisture-resistant film (8) is formed on the dielectric film (5) and the second electrode layer (6), and between the protective layer (9) and the first electrode layer (3) and the second electrode layer (Fig. 1 and [0044], note that a material of feature 8 of Takahashi is disclosed to be SiN and applicant has disclosed in [0052] of their specification that that SiN is a moisture resistant material). Takahashi discloses that the insulating layer (8) has the added benefit of preventing hydrogen generated in the post processes from entering the lower electrode, dielectric film, and upper electrode ([0044]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to provide the moisture resistant film of Takahashi in the invention of Harada in view of Armacost in order to prevent hydrogen generated by post processes from entering the underlying layers.
Claim(s) 7-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190122820 (Harada et al) in view of US 5622596 (Armacost et al) as applied to claim 6 above, and further in view of US 20030219956 (Mori et al).
Pertaining to claim 7, Harada in view of Armacost discloses forming the semiconductor device.
Harada in view of Armacost does not disclose further comprising, in a plan view in a thickness direction, a first resin body between the first outer electrode and the second outer electrode.
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However, Mori discloses a capacitor configuration (Figs. 9(a) and 9(b)) in which a resin body (11) in a plan view in a thickness direction, has a first resin body ([0049], #2 rectangular region in annotated Fig. 9(a) above) between the first outer electrode (10) and the second outer electrode (7). Mori discloses that this resin body configuration allows for probes of a measuring device to be brought in contact with the device to measure capacitance and allow for connection with subsequent conductive films to be form for incorporation to a printed circuit board ([0049]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Harada in view of Armacost to include the resin body configuration of Mori in order to allow for the formed device to be incorporated in a printed circuit board.
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As to claim 8, Harada in view of Armacost and Mori disclose wherein, in the thickness direction, a tip end of the first resin body is located at a position higher than tip ends of the first outer electrode and the second outer electrode (Mori Fig. 9(b), note that the tip end circled portion on feature 2 is higher than the top portion of outer electrodes 10 and 7).
Concerning claim 9, Harada in view of Armacost and Mori disclose wherein
the first resin body includes a first wall portion (Mori #2 rectangular region in annotated Fig. 9(a) above) proximal to the first outer electrode, and a second wall portion (Mori #3 rectangular region in annotated Fig. 9(a) above) proximal to the second outer electrode and separated from the first wall portion (Mori annotated Fig. 9(a), these bodies are separated by the oval portions noted in the annotated Fig. 9(a) above).
Continuing to claim 10, Harada in view of Armacost and Mori disclose wherein, in the plan view in the thickness direction, the first wall portion and the second wall portion are parallel to each other (Mori Fig. 9(b)).
Considering claim 11, Harada in view of Armacost and Mori disclose further
comprising, in the plan view in the thickness direction, a second resin body (Mori 11) between an end portion of the substrate and the first outer electrode (Mori #1 rectangular region in annotated Fig. 9(a) above), and between the end portion of the substrate and the second outer electrode (Mori #4 rectangular region in annotated Fig. 9(a) above).
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Regarding claim 12, Harada in view of Armacost and Mori disclose wherein, in the thickness direction, a tip end of the second resin body is located at a position higher than tip ends of the first outer electrode and the second outer electrode (Mori Fig. 9(b) note that the tip end circled portion on feature 1 is higher than the top portion of outer electrodes 10 and 7).
According to claim 13, Harada in view of Armacost and Mori discloses wherein, in the thickness direction, the tip end of the second resin body is located at a position lower than the tip end of the first resin body (Mori Fig. 9(b) note that the second resin body tip end circled portion on feature 1 is lower than the first resin body tip end of portion 2).
Referring to claim 14, Harada in view of Armacost and Mori disclose wherein the first resin body includes a first wall portion(Mori #2 rectangular region in annotated Fig. 9(a) above) proximal to the first outer electrode, and a second wall portion (Mori #3 rectangular region in annotated Fig. 9(a) above) proximal to the second outer electrode and separated from the first wall portion (Mori annotated Fig. 9(a) above), and the second resin body includes, in the plan view in the thickness direction, a first peripheral portion (Mori #1 rectangular region in annotated Fig. 9(a) above) along the end portion of the substrate and between the end portion of the substrate and the first outer electrode, and a second peripheral portion (Mori #4 rectangular region in annotated Fig. 9(a) above) along the end portion of the substrate and between the end portion of the substrate and the second outer electrode.
Referring to claim 15, Harada in view of Armacost and Mori disclose wherein the first wall portion and the first peripheral portion are connected to each other, and the second wall portion and the second peripheral portion are connected to each other (Mori annotated Fig. 9(a), note that the first wall and the first peripheral portion are connected to each other by the circular regions between them shown in the annotated Fig. 9(a) and the second wall and second peripheral portion are connected to each other by the circular
regions between them shown in the annotated Fig. 9(a)).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190122820 (Harada et al) in view of US 5622596 (Armacost et al) as applied to claim 1 above, and further in view of US 20110075317 (Oikawa et al).
Pertaining to claim 16, Harada in view of Armacost disclose forming a first electrode, a first outer electrode and a second outer electrode.
Harada in view of Armacost does not disclose further comprising: a third electrode layer on the dielectric film and separate from the second electrode layer, wherein the outer electrode is a first outer electrode connected to the third electrode layer, and the semiconductor device further comprises a second outer electrode connected to the second electrode layer. However, Oikawa discloses a capacitor configuration (Figs. 2A-2D) in which a first electrode (13) is formed and a dielectric layer (12) is formed over the first electrode and then a second and third electrode are formed over the dielectric layer (note that feature 13 is formed as two separate portions over dielectric layer 12) with two outer electrodes (14) connected to the electrode layers (Fig. 2D). Oikawa discloses that this configuration allows for a stable connection and increases production yield and improves the reliability of the device ([0034]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Harada in view of Armacost in order to provide a third electrode in the configuration as disclosed by Oikawa in order increase production yield and improve the reliability of the device.
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190122820 (Harada et al) in view of US 5622596 (Armacost et al) as applied to claim 1 above, and further in view of US 20190172773 (Kurokawa et al).
As to claims 17 and 18, Harada in view of Armacost disclose forming a semiconductor device and more specifically a capacitor structure.
Harada in view of Armacost does not disclose the use of the explicit use of semiconductor device and therefore does not disclose a matching circuit comprising the semiconductor device or a filter circuit comprising the semiconductor device. However, Kurokawa discloses the use of a capacitor device in filter circuits ([0116] and [0141]) and matching circuits ([0117] and [0141]). Ryco, Inc. v. Ag-Bag Corp., 857 F.2d 1418, 8 USPQ2d 1323 (Fed. Cir. 1988) See MPEP 2144.07. The selection of a known device based on its suitability for its intended use supported a prima facie obviousness determination. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use the semiconductor device of Harada in view of Armacost as a capacitor device in Kurokawa because of its known suitability for use as a capacitor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20210020738 discloses a capacitor device (Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VALERIE N NEWTON/ Examiner, Art Unit 2897 02/05/26
/CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897