DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/06/2023 was filed after the mailing date of the application on 11/06/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention I drawn out to claims 1-9 and 20 in the reply filed on 02/11/2026 is acknowledged.
Claims 10-19 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/11/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 5; claim 5 contains the limitations: “…and an upper surface of the gap fill insulating layer is level with a highest point of the upper surface of the top die according to the accumulated topology.” (emphasis added). The language used in describing this limitation nor any similar language that might lead to a similar understanding of the limitation reasonably, are absent from the specification and are not depicted in any of the figures provided in the disclosure.
Claims 6-7 are rejected under 35 U.S.C. 112(a) for their dependence on claim 5.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitation indicate claim limitations that are not explicitly disclosed by the primary reference but are disclosed by the secondary reference(s)
Claims 1, 8-9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al, US 20220181232 A1 (Jeng) in view of Chen et al, US 20220139882 A1 (Chen).
Regarding claim 1; Jeng teaches a semiconductor package comprising:
a package substrate (Jeng: Annotated Fig (4G) shared in this OA: Substrate containing the interconnect structure 110);
a stack die (130a, 130b) including a plurality of dies (132A, 132B, 132C, 132D) are stacked on the package substrate (Substrate containing the interconnect structure 110);
a gap fill insulating layer (170) on an upper surface of the stack die (130a, 130b);
a top dummy die on the gap fill insulating layer (170);
and a molding portion (150) surrounding the stack die (130a, 130b) having the top dummy die thereon.
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Jeng does not teach a top dummy die; and a molding portion surrounding the stack die having the top dummy die thereon
However, Chen teaches a top dummy die (Chen: Fig (5F): 108); and a molding portion (210) surrounding the stack die (102) having the top dummy die (108) thereon.
Jeng and Chen are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jeng by using a dummy die on top of the die stack to increase the rigidity of the die stack and its ability to withstand mechanical stresses leading to a more reliable device.
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Regarding claim 8; Jeng in view of Chen teaches all the limitations of the semiconductor package of claim 1.
Further, Jeng teaches further comprising: a gap fill sidewall structure (Jeng: Annotated Fig (4G): 140) connected to the gap fill insulating layer (170) and surrounding a side surface of the stack die (130a, 130b).
Regarding claim 9; Jeng in view of Chen teaches all the limitations of the semiconductor package of claim 8.
Further, Jeng teaches wherein the molding portion (Jeng: Annotated Fig (4G) shared in this OA: 150) surrounds the gap fill sidewall structure (140) of the stack die (130a, 130b).
Regarding claim 20; Jeng teaches a semiconductor package comprising:
a package substrate (Jeng: Annotated Fig (4G) shared in this OA: Substrate containing the interconnect structure 110);
a stack die (130a, 130b) including a plurality of dynamic random access memory (DRAM) chips ([0021]) stacked on the package substrate (Substrate containing the interconnect structure 110);
a gap fill insulating layer (170) on an upper surface of the stack die (130a, 130b);
a gap fill sidewall structure (140) on a side surface of the stack die (130a, 130b);
a top dummy die on the gap fill insulating layer (170);
and a molding portion (150) surrounding the gap fill sidewall structure (140) of the stack die (130a, 130b).
Jeng does not teach a top dummy die.
However, Chen teaches a top dummy die (Chen: Fig (5F): 108).
Jeng and Chen are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jeng by using a dummy die on top of the die stack to increase the rigidity of the die stack and its ability to withstand mechanical stresses leading to a more reliable device.
Claims 2-7 are rejected under 35 U.S.C. 103 as being unpatentable over Jeng et al, US 20220181232 A1 (Jeng) in view of Chen et al, US 20220139882 A1 (Chen) in further view of Shin, US 20230113020 A1 (Shin)
Regarding claim 2; Jeng in view of Chen teaches all the limitations of the semiconductor package of claim 1.
Jeng in view of Chen does not teach wherein the gap fill insulating layer is formed by a spin on deposition process.
Shin teaches wherein the gap fill insulating layer (213) is formed by a spin on deposition process ([0068]: “In some embodiments, the passivation layer 213 may be formed by, for example, spin-coating, lamination, deposition, or the like.”).
Jeng in view of Chen and Shin are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jeng in view of Chen by using a spin coating method to deposit the gap fill insulating layer as disclosed in Shin to better streamline the device production process through adopting methods that interweave well with other photolithography processes making the device production more efficient.
Regarding claim 3; Jeng in view of Chen in further view of Shin teach all the limitations of the semiconductor package of claim 2.
Jeng does not teach wherein the gap fill insulating layer includes at least one of TEOS, PSG, BPSG, USG, PE-TEOS, and an HDP-CVD oxide
However, Chen teaches wherein the gap fill insulating layer (Chen: Fig (5F): 107) includes at least one of TEOS ([0053]), PSG, BPSG, USG, PE-TEOS, and an HDP-CVD oxide.
Jeng and Chen are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jeng by making the gap fill insulating layer out of TEOS as disclosed in Chen to improve the electrical insulation of the die stack leading to a more reliable device.
Regarding claim 4; Jeng in view of Chen in further view of Shin teaches all the limitations of the semiconductor package of claim 2.
Further, Jeng teaches wherein a thickness of the gap fill insulating layer (Jeng: Annotated Fig (4G) shared in this OA: 170) covers a surface step difference of an upper surface of a top die (132D) in the stack die (130a, 130b) according to an accumulated topology of the stack die (130a, 130b).
Regarding claim 5; Jeng in view of Chen in further view of Shin teaches all the limitations of the semiconductor package of claim 4.
Further, Jeng teaches wherein the gap fill insulating layer (Jeng: Annotated Fig (4G) shared in this OA: 170) is an oxide, and an upper surface of the gap fill insulating layer (170) is level with a highest point of the upper surface of the top die (132D) according to the accumulated topology.
However, Jeng does not teach that the gap fill insulating layer is an oxide.
Chen teaches that the gap fill insulating layer (Chen: Fig (5F): 107) is an oxide ([0053]).
Jeng and Chen are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to construct the gap fill insulating layer as an oxide to improve its insulation properties leading to a more reliable device.
Regarding claim 6; Jeng in view of Chen in further view of Shin teaches all the limitations of the semiconductor package of claim 5.
Further, Jeng teaches wherein the gap fill insulating layer (Jeng: Annotated Fig (4G) shared in this OA: 170) has a planarized upper surface.
Regarding claim 7; Jeng in view of Chen in further view of Shin teaches all the limitations of the semiconductor package of claim 6.
Further, Jeng teaches further comprising: an adhesive member (Jeng: Annotated Fig (4G) shared in this OA: 170), wherein the adhesive member (170) connects the top dummy die to the planarized upper surface of the gap fill insulating layer (170).
Jeng does not teach a top dummy die.
However, Chen teaches a top dummy die (Chen: Fig (5F): 108).
Jeng and Chen are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Jeng by using a dummy die on top of the die stack to increase the rigidity of the die stack and its ability to withstand mechanical stresses leading to a more reliable device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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