Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/502,759 filed November 6, 2023. Claims 1-17 are currently pending and have been considered below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 & 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arata (Japanese Publication 2019110244).
Regarding claim 1, Arata discloses a semiconductor device comprising:
a first semiconductor element (Fig. 1, 110) including a first electrode (Paragraph [0014]);
a first object (130) including a first surface facing the first electrode;
a sealing resin (330) covering the first semiconductor element and the first object; and
a covering part (310) interposed between the first electrode and the first surface and containing a material having a higher thermal conductivity than the sealing resin (Paragraph [0017]).
Regarding claim 2 & 3, Arata further discloses:
The covering part contains a metal such as Ag or Cu (Paragraph [0019]).
Regarding claim 14 & 15, Arata further discloses:
a first wire (150) including a bonding part bonded to the first electrode (Paragraph [0014]) wherein the covering part (310) is in contact with the bonding part (Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arata (Japanese Publication 2019110244) in view of Gowda (Pre-Grant Publication 2017/0263539).
Regarding claim 4, Arata discloses all of the limitations of claim 3 (addressed above). Arata does not explicitly disclose the covering part contains sintered Ag or sintered Cu. However Gowda disclose a semiconductor device comprising:
A plurality of semiconductor elements (Fig. 3, 43-46) wherein a covering part/thermal interface layer (82) is formed over the semiconductor elements and a first object (66) formed over the covering part/thermal interface layer wherein the thermal interface layer can be sintered Ag/silver (Paragraph [0043]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the covering part to contain sintered Ag or Cu because sintered Ag or Cu are well known material allowing for high reliability in bonding and allow for high heat dissipation from semiconductor devices.
Claim(s) 5 & 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arata (Japanese Publication 2019110244) in view of Kajiwara (Pre-Grant Publication 2014/0264383).
Regarding claims 5 & 17, Arata discloses all of the limitations of claim 1 (addressed above). Arata further discloses:
The first semiconductor element (110) has switching function (Paragraph [0009])
Arata does not explicitly disclose the first electrode is a source electrode and the electrode contains Al. However Kajiwara discloses a semiconductor device comprising:
A semiconductor chip (Fig. 2, 1) wherein a source electrode (2) is formed on the chip and can contain Aluminum (Paragraph [0054]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the electrode as source electrode containing aluminum because the source electrode can serve in operation of the chip which can be a MOSFET/transistor based device wherein aluminum is a commonly used conductive material to establish an conductive path between the chip and an external electrode.
Claim(s) 6-7, 9, 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arata (Japanese Publication 2019110244) in view of Solimando (Pre-Grant Publication 2017/0294422).
Regarding claim 6-7, 9, 11-12, Arata disclose all of the limitations of claim 1 (addressed above). Arata does not disclose the first object includes a second semiconductor device and includes an insulating layer interposed between the second semiconductor element and the covering part. However Solimando discloses a semiconductor device comprising:
A first semiconductor element (Fig. 2, 211) wherein a covering part/thermal interface material (270) and a first object (202) including a second semiconductor element (221), an insulating layer (222) interposed between the second semiconductor and covering part, and a conductive member (223) containing a metal.
It would have been obvious to those having ordinary skill in the art at the time of invention to form the first object to include a second semiconductor element, insulating layer and conductive member because it will form a second package coupled and communicative with a lower package such as stacked memory/logic package wherein data/signal can be transferred between the first and second semiconductor devices (Paragraph [0031], [0037], [0041]).
Claim(s) 8 & 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arata (Japanese Publication 2019110244) in view of Solimando (Pre-Grant Publication 2017/0294422) as applied to claim 7 & 9 above, and further in view of Gowda (Pre-Grant Publication 2017/0263539).
Regarding claim 8 & 10, Arata and Solimando disclose all of the limitations of claim 7 & 9 (addressed above). Neither reference explicitly disclose the insulating layer contains an ceramic material or Si. However Gowda discloses a semiconductor device comprising:
A ceramic insulator layer (Fig. 3, 84) form between the thermal insulator (82) and first object/heat sink (66).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the insulating layer as an ceramic insulator because it will provide additional isolation for high voltage applications between the semiconductor module package and the heat sink (Paragraph [0041]).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arata (Japanese Publication 2019110244) in view of Solimando (Pre-Grant Publication 2017/0294422) as applied to claim 9 above, and further in view of Inoue (Pre-Grant Publication 2019/0295933).
Regarding claim 13, Arata and Solimando disclose all of the limitations of claim 9 (addressed above). Neither reference explicitly disclose the first object includes a second surface facing away from the first surface and exposed from the sealing resin. However Inoue disclose a semiconductor device comprising:
A first semiconductor element (Fig. 1b, 15) and a first object/ metal member (16) wherein the first object has a surface exposed from mold resin material (30) (Paragraph [0030]).
It would have been obvious to those having ordinary skill in the art at the time of invention to expose the surface of the first object from the mold resin because it will allow the metal member to function as a heat dissipating plate and effectively remove heat from the semiconductor element to the outside environment.
Allowable Subject Matter
Claim 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 16 is considered allowable because none of the prior art either alone or in combination discloses the bonding part is located between the first electrode and the first object.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818