Prosecution Insights
Last updated: October 01, 2026
Application No. 18/502,862

STACK OF MONOCRYSTALLINE LAYERS FOR PRODUCING MICROELECTRONIC DEVICES WITH 3D ARCHITECTURE

Non-Final OA §102§103§112
Filed
Nov 06, 2023
Priority
Nov 08, 2022 — FR 2211627
Examiner
WARD, ERIC A
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
589 granted / 754 resolved
+10.1% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
24 currently pending
Career history
774
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
58.4%
+18.4% vs TC avg
§102
21.0%
-19.0% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 754 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 8-11,14,16-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species as , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/01/2026. Claim Objections Claims 4,13,14,16,18,20 are objected to because of the following informalities: Claim 4 line 2 “5.1019at/cm3” should be “5x1019at/cm3”; Claim 13 line 14 recites step d) depositing at least one second dielectric material […] which should be f) as step d) is previously recited in lines 9-11; Claim 14 line 14 recites step d) depositing at least one second dielectric material […] which should be f) as step d) is previously recited in lines 9-11; Claim 16 line 7 recites step e) selectively etching […] which should be c) as step e) is later claimed in lines 12-16. Claim 18 line 7 recites step e) which should be c) as step e) is later claimed in lines 12-13; Claim 20 line 8 recites step e) which should be c) as step e) is later claimed in lines 12-16. Claims 14,16,18 are withdrawn but the objections are documented such that Applicants may amend the claims (using the appropriate status identifier of “(Withdrawn – Currently Amended)” as per 37 C.F.R. 1.121 and MPEP 714) in order to place the claims in condition such that they may be eligible for rejoinder should they be found to depend from or otherwise require all the limitations of an allowable claim, rejoinder being considered when all claims are otherwise in condition for allowance, see MPEP 821.04. Additionally, claim 16 line 18 in step h) refers back to “the selective etching in step e)” but claim 16 includes two steps e) in lines 8-9 and 12-16 and therefore it is unclear which selective etching step e) is being referred to claim 16, and therefore will not be eligible for rejoinder in the present form which includes antecedent basis indefiniteness issue. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 20 recites two steps e) in lines 8-9 and 12-16 and therefore claim 20 line 18 which refers back to step e) is indefinite. For purposes of examination, claim 20, the first step e) in lines 8-9 is interpreted as step c). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2019/0172755 A1 to SMITH et al., “Smith”. Regarding claim 1, Smith discloses (FIG. 2A) a stack of layers suitable for producing a microelectronic device with 3D architecture comprising transistors (¶ [0024]-[0029]), said stack including plural first layers (130, ¶ [0036]) of unintentionally doped silicon, plural second layers (110) of unintentionally doped SiGe, and at least one third layer (middle 120) of P-doped silicon (“Si:B” is boron-doped silicon and boron is a p-type dopant), such that said first layers (130), said second layers (110) and said at least one third layers (120) are stacked one above the other, said at least one third layer (130) having a so-called "lower" side arranged on and in contact with a given semiconductor layer (e.g. 130) among said first layers or second layers or being arranged on and in contact with a semiconductor layer of a substrate (“Si”), said at least one third layer (120) having a so- called "upper" side opposite said lower side, said upper side being arranged below and in contact with another semiconductor layer (e.g. 110) among said first layers or second layers. Examiner’s Note: a person having ordinary skill in the art (“PHOSITA”) would recognize that a layer identified as Si or SiGe to be undoped or unintentionally doped when contrasted with another layer being described as doped (e.g. “Si:B or a doped silicon” ¶ [0036]) or when contrasted with other embodiments where layers are described as doped (e.g. FIG. 3A has Doped Si). Regarding claim 2, Smith discloses the stack according to claim 1, and Smith further discloses (FIG. 2A) said stack (of FIG. 2A) being entirely made up of three different semiconductor materials (130, 120, and 110 as pictured). Regarding claim 3, Smith discloses the stack according to claim 2, and Smith further discloses (FIG. 2A) the stack being entirely made up of first layers (130) of unintentionally doped silicon, second layers (110) of unintentionally doped SiGe, and at least one third layer (120) of P-doped silicon. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0172755 A1 to SMITH et al., “Smith”, in view of US 2010/0295021 A1 to Chang et al., “Chang”. Regarding claim 4, although Smith discloses the stack of layers according to claim 1, Smith fails to clearly state wherein the silicon or SiGe of the third layer has a concentration of P-type dopants greater than or equal to 5.10¹⁹ at/cm³. Chang teaches wherein a sacrificial SiGe layer (107) contains a high concentration of dopants (either n-type or p-type) in concentrations of from about 1x1019 atoms per cubic centimeter (atoms/cm3) to about 1x1022 atoms/cm3 may be employed (¶ [0029]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the stack of Smith with the concentration of p-type dopants within the claimed range as taught by Chang in order to selectively dope the adjacent nanosheet layers for forming n-type and p-type transistors (Chang ¶ [0029]) and/or in order to achieve high selectivity (Chang ¶ [0060]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the concentration determines the etch selectivity (Smith ¶ [0037]) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0172755 A1 to SMITH et al., “Smith”, in view of US 2019/0165135 A1 to Cheng et al., “Cheng”. Regarding claim 5, although Smith discloses the stack of layers according to claim 1, Smith fails to clearly state wherein the intrinsic SiGe has a germanium concentration greater than or equal to 10% and less than 50%. Smith teaches (FIG. 2A to 2B) trimming the intrinsic SiGe layer (110, ¶ [0038]). Cheng teaches (e.g. FIG. 7 to FIG. 8) forming SiGe layers (18e,22-1,22-2) with varying concentration of germanium including Ge from 15-40% (¶ [0021],[0022]) since increased Ge concentration increases the etch rate (¶ [0021],[0023]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the stack of Smith with the intrinsic SiGe layers having Ge within the claimed range as taught by Cheng in order to desirably control the etch rate and etch amount during Smith’s trimming step (Cheng ¶ [0021]) since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the concentration determines the etch selectivity making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0172755 A1 to SMITH et al., “Smith”, in view of US 2022/0310456 A1 to Hall et al. cited in IDS, “Hall”. Regarding claim 6, although Smith discloses the stack of layers according to claim 1, Smith fails to clearly state wherein the number of first layers or second layers is comprised between 4 and 300. Hall teaches wherein the number of silicon nanosheets may be decreased or increased (e.g. 4 Si nanosheets instead of 2 Si nanosheets) in order to optimize transistor performance (¶ [0073]). It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the stack of Smith with four (4) first or second layers as taught by Hall in order to optimize transistor performance (Hall ¶ [0073]) since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the number of layers determines the number of channels which determines the transistor characteristics such as current throughput making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized. Allowable Subject Matter Claims 7,12-13,15,19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Prior art e.g. Smith teaches a including a doped Si layer as an etch-selectable layer among a plurality of undoped Si and undoped SiGe layers as discussed above. US 9,935,014 B1 to Cheng et al. teaches wherein a stack is formed to include a doped semiconductor layer (Fig. 2 layer 202, column 7 lines 10-43). Prior art e.g. US 2020/0176326 A1 to Liao et al. teaches (e.g. Figure 7) forming a plurality of first (70A) and second (70B) doped semiconductor layers (¶ [0027]). Prior art e.g. US 2016/0111284 A1 to Kittl et al. teaches (e.g. FIG. 2A) including a plurality of layers (B) contacting a third layer (A). However, prior art fails to reasonably teach or suggest wherein each of the first and second layers is arranged between two third layers and is in contact with these two third layers, as claimed in claim 7 together with all of the limitations of claim 1. Claims 12-13,15,19, (claim 20 insofar as definite) are objected to as being allowable insofar as they depend upon and include all of the limitations of claim 7. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2017/0025314 A1 to Witters et al. teaches (e.g. Fig. 1(a) to 1(c)) using etch selectable silicon (Si) and silicon-germanium (SiGe) layers in order to form a stack of Ge layer (Fig. 1(c)) Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Eric A. Ward/Primary Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Nov 06, 2023
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
91%
With Interview (+13.3%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 754 resolved cases by this examiner. Grant probability derived from career allowance rate.

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