Prosecution Insights
Last updated: May 29, 2026
Application No. 18/502,883

PLATED STANDOFF FEATURE FOR PROVIDING STANDOFF BETWEEN CIRCUIT BOARD AND CIRCUIT PACKAGE

Non-Final OA §102§103
Filed
Nov 06, 2023
Examiner
WILLIS, TREMESHA S
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
DELL PRODUCTS, L.P.
OA Round
4 (Non-Final)
78%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
685 granted / 879 resolved
+9.9% vs TC avg
Strong +17% interview lift
Without
With
+17.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
36 currently pending
Career history
920
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.6%
+6.6% vs TC avg
§102
50.5%
+10.5% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 879 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment/Arguments Applicant's arguments with respect to claims 1 – 12 have been considered, and have found to be persuasive. Please see the new ground(s) of rejection below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (U.S. Patent Publication No. 2024/0244761). Regarding claim 1, in Figure 5, Wang discloses an information handling resource comprising: a circuit board (110) comprising an electrically-conductive pad (112); and a plated standoff (120) plated (this is an apparatus claim, thus the method of forming the standoff on the pad holds no patentable weight) onto a surface of the electrically-conductive pad (Figure 5). Regarding claim 2, Wang discloses a circuit package (130) comprising an electrically-conductive pin (134); and reflowed solder (solder not shown; the solder column 120 is soldered to the connector 134, paragraph [0034], which means the solder is also electrically coupling the pad 112 to the connector 134) electrically coupling the electrically-conductive pad (112) to the electrically-conductive pin (Figure 5). Regarding claim 3, Wang discloses wherein the circuit package is a bottom-terminated component (Figure 5). Regarding claim 4, Wang discloses wherein the plated standoff is cylindrical in shape (Figure 5). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 5 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang. Regarding claim 5, in Figure 5, Wang discloses an information handling system comprising: a processor (130); and an information handling resource comprising: a circuit board (110) comprising an electrically-conductive pad (112); and a plated standoff (120) plated (this is an apparatus claim, thus the method of forming the standoff on the pad holds no patentable weight) onto a surface of the electrically-conductive pad (Figure 5). Wang does not specifically disclose package 130 being a processor. However, providing a semiconductor package/chip with processing capability is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill. Regarding claim 6, Wang discloses a circuit package comprising an electrically-conductive pin (134, Figure 5); and reflowed solder (solder not shown; the solder column 120 is soldered to the connector 134, paragraph [0034], which means the solder is also electrically coupling the pad 112 to the connector 134) electrically coupling the electrically-conductive pad (112) to the electrically-conductive pin (Figure 5). Regarding claim 7, Wang discloses wherein the circuit package is a bottom-terminated component (Figure 5). Regarding claim 8, Wang discloses wherein the plated standoff is cylindrical in shape (Figure 5). Regarding claim 9, in Figure 5, Wang discloses a method comprising: forming a circuit board (110) with an electrically-conductive pad (112); and plating a plated standoff (120) onto a surface of the electrically-conductive pad (Figure 5). Wang does not specifically disclose solder column 120 being plated onto the pad 112. However, forming a solder column/standoff on the surface of a conductive pad via plating is common place and well known in the art, and is merely a design option for a skilled artisan without the exercise of inventive skill. Regarding claim 10, Wang discloses electrically coupling an electrically-conductive pin (134, Figure 5) of a circuit package (130) to the electrically-conductive pad (112) with reflowed solder (solder not shown; the solder column 120 is soldered to the connector 134, paragraph [0034], which means the solder is also electrically coupling the pad 112 to the connector 134). Regarding claim 11, Wang discloses wherein the circuit package is a bottom-terminated component (Figure 5). Regarding claim 12, Wang discloses forming the plated standoff such that the plated standoff is cylindrical in shape (Figure 5). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Show 3 earlier events
Oct 20, 2025
Examiner Interview Summary
Oct 20, 2025
Applicant Interview (Telephonic)
Oct 21, 2025
Response Filed
Jan 08, 2026
Non-Final Rejection mailed — §102, §103
Feb 18, 2026
Response Filed
Mar 02, 2026
Final Rejection mailed — §102, §103
Apr 15, 2026
Response after Non-Final Action
Apr 29, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.3%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 879 resolved cases by this examiner. Grant probability derived from career allowance rate.

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