Prosecution Insights
Last updated: July 17, 2026
Application No. 18/503,138

MANUFACTURING METHOD OF ELECTRONIC DEVICE AND ELECTRONIC DEVICE

Final Rejection §103
Filed
Nov 06, 2023
Priority
Dec 02, 2022 — provisional 63/429,555 +1 more
Examiner
VARGHESE, ROSHN K
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
2 (Final)
67%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
506 granted / 754 resolved
-0.9% vs TC avg
Strong +21% interview lift
Without
With
+20.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
25 currently pending
Career history
788
Total Applications
across all art units

Statute-Specific Performance

§103
91.2%
+51.2% vs TC avg
§102
5.2%
-34.8% vs TC avg
§112
2.8%
-37.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 754 resolved cases

Office Action

§103
CTFR 18/503,138 CTFR 87635 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Arguments Applicant’s arguments with respect to claim(s) 11 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 11, 12 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Boemmels (US 2009/0085173 A1) in view of Kawano (US 2010/0326709 A1) . Regarding Claim 11 , Boemmels (US 2009/0085173 A1) discloses an electronic device (Fig 3), comprising: a substrate (301); a first conductive layer (302), disposed on the substrate (301); a first insulating layer (303), disposed on the first conductive layer (302), wherein the first insulating layer (303) has a via (305) exposing a part of the first conductive layer (302); and a second conductive layer ([0008-0011,0030-0031] “seed layer deposited on the barrier layer”, “copper”), disposed on the first insulating layer (303), and an electrical connection layer (309), disposed in the via (305) of the first insulating layer (303), wherein the electrical connection layer (309) is electrically connected ([0008,0030]) to the first conductive layer (302) and the second conductive layer ([0008-0011,0030-0031] “seed layer deposited on the barrier layer”, “copper”; note that copper is electrically conductive), and the electrical connection layer (309) covers the second conductive layer ([0008-0011,0030-0031] “seed layer deposited on the barrier layer”, “copper”); wherein an aspect ratio ([0030]) of the via (305) of the first insulating layer (303) is greater than 1 ([0030]), wherein at least part of a sidewall (see Fig 3c; sidewall is directly and indirectly covered by 308) of the first insulating layer (303) is covered by the second conductive layer (308). Boemmels does not explicitly disclose the electrical connection layer covers the second conductive layer on the sidewall of the first insulating layer and wherein the electrical connection layer is in contact with the first conductive layer and/or the first insulating layer. Kawano (US 2010/0326709 A1) teaches of an electronic device (Fig 2), comprising: a substrate (11); a first conductive layer (14), disposed on the substrate (11); a first insulating layer (111), disposed on the first conductive layer (14), wherein the first insulating layer (111) has a via (at 16) exposing (see Fig 5) a part of the first conductive layer (14); and a second conductive layer (32), disposed on the first insulating layer (111), and an electrical connection layer (17), disposed in the via (16) of the first insulating layer (111), wherein the electrical connection layer (17) is electrically connected to the first conductive layer (14) and the second conductive layer (32), and the electrical connection layer (17) covers the second conductive layer (32) on the sidewall of the first insulating layer (111); wherein at least part of a sidewall (see Fig 2B; sidewall is directly and indirectly covered by 32) of the first insulating layer (111) is covered by the second conductive layer (32); wherein the electrical connection layer (17) is in contact ([0032-0033]) with the first conductive layer (14) and/ or the first insulating layer. It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as disclosed by Boemmels, wherein the electrical connection layer covers the second conductive layer on the sidewall of the first insulating layer and wherein the electrical connection layer is in contact with the first conductive layer as taught by Kawano, in order to prevent copper ion migration, prevent cracks, provide adhesion, and in order to provide lower electrical resistance and excellent electrical characteristics (Kawano, [0032-0037,0061,0062]). Regarding Claim 12 , Boemmels further discloses the electronic device (Fig 3) according to claim 11, wherein the second conductive layer (308) covering the at least part of the sidewall of the first insulating layer (303) is a continuous film layer (see Fig 3c showing 308,309 is a continuous film layer). Regarding Claim 16 , Boemmels further discloses the electronic device (Fig 3) according to claim 11, further comprising a buffer layer (308) disposed between the first insulating layer (303) and the second conductive layer ([0008-0011,0030-0031] “seed layer deposited on the barrier layer”, “copper”), and located on a top surface of the first insulating layer (303) . 07-22-aia AIA Claim (s) 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Boemmels (US 2009/0085173 A1) in view of Kawano (US 2010/0326709 A1) as applied to claim 16 above, and further in view of Kondo (US 2009/0288870 A1) . Regarding Claim 17 , Boemmels in view of Kawano teaches the limitations of the preceding claim. Boemmels does not disclose the electronic device according to claim 16, wherein a roughness of a top surface of the buffer layer is less than a roughness of the sidewall of the first insulating layer. Kondo (US 2009/0288870 A1) teaches of a roughness of a top surface (upper surface of 30) of a layer (30; [0064]) is less than a roughness ([0064]) of a sidewall (at VH) of a first insulating layer (30). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Boemmels in view of Kawano, wherein a roughness of a top surface of the layer is less than a roughness of the sidewall of the first insulating layer as taught by Kondo, in order to provide reliability and improve miniaturization (Kondo, [0013,0018,0023,0064]) and furthermore since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art in order to provide reliability and improve miniaturization, such that a roughness of a top surface of the buffer layer is less than a roughness of the sidewall of the first insulating layer. In re Boesch , 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, page 25, [0102], Applicant has not disclosed any criticality for the claimed limitations. Regarding Claim 18 , Boemmels in view of Kawano teaches the limitations of the preceding claim. Boemmels does not disclose the electronic device according to claim 16, wherein a roughness of the top surface of the first insulating layer is less than a roughness of the sidewall of the first insulating layer. Kondo (US 2009/0288870 A1) teaches of a roughness of a top surface (upper surface of 30) of a first insulating layer (30; [0064]) is less than a roughness ([0064]) of a sidewall (at VH) of the first insulating layer (30). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Boemmels in view of Kawano, wherein a roughness of the top surface of the first insulating layer is less than a roughness of the sidewall of the first insulating layer as taught by Kondo, in order to provide reliability and improve miniaturization (Kondo, [0013,0018,0023,0064]) and furthermore since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art in order to provide reliability and improve miniaturization. In re Boesch , 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, page 24, [0099] Applicant has not disclosed any criticality for the claimed limitations . . 07-22-aia AIA Claim (s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Boemmels (US 2009/0085173 A1) in view of Kawano (US 2010/0326709 A1) as applied to claim 11 above, and further in view of Sakai (US 2016/0316558 A1) . Regarding Claim 19 , Boemmels in view of Kawano teaches the limitations of the preceding claim. Boemmels does not disclose the electronic device according to claim 11, wherein a roughness of a top surface of the electrical connection layer is less than a roughness of the sidewall of the first insulating layer. Sakai (US 2016/0316558 A1) teaches of an electronic device (Fig 1) wherein a roughness (Ra3; [0033-0036]) of a top surface of an electrical connection layer (21) is less than ([0033-0036]) a roughness (Ra1) of a sidewall (25b) of a first insulating layer (30). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Boemmels in view of Kawano, wherein a roughness of a top surface of the electrical connection layer is less than a roughness of the sidewall of the first insulating layer as taught by Sakai, in order to improve contact area, prevent likelihood of peeling, prevent an unstable connection, and prevent problems related to contact resistance (Sakai, [0033-0036]). Please note that in the instant application, page 25 [0101], applicant has not disclosed any criticality for the claimed limitations . 07-22-aia AIA Claim (s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Boemmels (US 2009/0085173 A1) in view of Kawano (US 2010/0326709 A1) as applied to claim 11 above, and further in view of Noto (US 2018/0213644 A1) . Regarding Claim 20 , Boemmels in view of Kawano teaches the limitations of the preceding claim. Boemmels does not disclose the electronic device according to claim 11, wherein an included angle between the sidewall of the first insulating layer and a top surface and/or a bottom surface of the first insulating layer is greater than or equal to 80 degrees and less than or equal to 100 degrees. Noto (US 2018/0213644 A1) teaches of an electronic device (Fig 1B), wherein an included angle (θ1) between a sidewall (60W) of a first insulating layer (50A) and a top surface and/or a bottom surface (surface at bottom of 50A at 34) of the first insulating layer is greater than or equal to 80 degrees ([0017]) and less than or equal to 100 degrees. It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the device as taught by Boemmels in view of Kawano, wherein an included angle between the sidewall of the first insulating layer and a top surface and/or a bottom surface of the first insulating layer is greater than or equal to 80 degrees and less than or equal to 100 degrees as taught by Noto, in order to prevent breaks and reduce effects of stress concentrations (Noto, [0017]) and furthermore since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art in order to prevent breaks and reduce effects of stress concentrations. In re Boesch , 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Please note that in the instant application, page 22 [0092], Applicant has not disclosed any criticality for the claimed limitations . . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Wakizaka (US 2004/0237295 A1) teaches of an electronic device (Fig 1-6), comprising: a substrate (1); a first conductive layer (2), disposed on the substrate (1); a first insulating layer (3), disposed on the first conductive layer (2), wherein the first insulating layer (3) has a via (6) exposing a part of the first conductive layer; and a second conductive layer (8), disposed on the first insulating layer, wherein the second conductive layer (8) is electrically connected to the first conductive layer (2) through the via (6) of the first insulating layer. This could be used in a 103 Rejection . Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROSHN K VARGHESE/ Primary Examiner, Art Unit 2847 Application/Control Number: 18/503,138 Page 2 Art Unit: 2847 Application/Control Number: 18/503,138 Page 3 Art Unit: 2847 Application/Control Number: 18/503,138 Page 4 Art Unit: 2847 Application/Control Number: 18/503,138 Page 5 Art Unit: 2847 Application/Control Number: 18/503,138 Page 6 Art Unit: 2847 Application/Control Number: 18/503,138 Page 7 Art Unit: 2847 Application/Control Number: 18/503,138 Page 8 Art Unit: 2847 Application/Control Number: 18/503,138 Page 9 Art Unit: 2847 Application/Control Number: 18/503,138 Page 10 Art Unit: 2847 Application/Control Number: 18/503,138 Page 11 Art Unit: 2847
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Prosecution Timeline

Nov 06, 2023
Application Filed
Jan 09, 2026
Non-Final Rejection mailed — §103
Apr 02, 2026
Response Filed
Jun 04, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
67%
Grant Probability
88%
With Interview (+20.6%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 754 resolved cases by this examiner. Grant probability derived from career allowance rate.

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