DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 2019/0042160 A1), and further in view of Kodama (US 2010/0054052 A1).
Regarding claims 1, Kumar teaches a method for operating a memory device which includes at least one memory unit, wherein the at least one memory unit includes a bistable multivibrator, and two access transistors for controllable connection of the bistable multivibrator to two secondary control lines associated with the at least one memory unit, wherein the connection of the bistable multivibrator to the two secondary control lines is controllable using a first primary control line, the method comprising the following steps: applying a control signal to a control terminal of at least one of the two access transistors; and determining a first variable which characterizes at least one current flowing through the load path of the at least one access transistor (Kumar teaches a bistable memory cell Fig. 1B. During the access operation, a voltage is applied to the word line WL. Read and write data are accessed through the bit lines BL and BL_B when signal is applied to the word line WL to access the memory cell. The memory system uses a time to digital conversion (TDC) to sense the current in the bit line to determine the variable (e.g. whether data is 0 or 1) based on the current flowing through the bit lies, Fig. 2A to Fig. 2C).
Kumar teaches applying a high voltage to active the word line. Kumar is silent in teaching applying a control signal to a control terminal of at least one of the two access transistors in such a way that, in accordance with a first magnitude of the control signal, a load path of the at least one access transistor is at least partially electrically conductive by the first magnitude placing the load path in a first resistance state, the load path when in the first-resistance state being less electrically conductive than when, in accordance with a second magnitude of the control signal, the load path is placed in a second resistance state, a resistance of the first-resistance state being higher than a resistance of the second-resistance state.
Kodama teaches applying a control signal to a control terminal of at least one of the two access transistors in such a way that, in accordance with a first magnitude of the control signal, a load path of the at least one access transistor is at least partially electrically conductive by the first magnitude placing the load path in a first resistance state, the load path when in the first-resistance state being less electrically conductive than when, in accordance with a second magnitude of the control signal, the load path is placed in a second resistance state, a resistance of the first-resistance state being higher than a resistance of the second-resistance state (Fig. 3 and Fig. 11, teaches applying different voltages to active the word line. The word line driver will apply a first voltage Vbase, which will partially turn on the NMOS transistor. The word line driver will apply a second voltage (j) which is higher than the first voltage which will open the NMOS transistor more than the first voltage Vbase and the first voltage will be less electrically conductive than the second voltage).
It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to Kodama’s word line driver in order to have a stable operation.
Regarding claim 2, Kumar further teaches the method according to claim 1, wherein the memory unit is a memory cell (Fig. 1B).
Regarding claim 3, Kumar further teaches the method according to claim 1, wherein the second control lines are bit lines (Fig. 1B, BL or BL_b).
Regarding claim 4, Kumar further teaches the method according to claim 1, wherein the first primary control line is a word line (Fig. 1B, WL).
Regarding claim 5, Kumar further teaches the method according to claim 1, wherein the application of the control signal to the control terminal of the at least one of the two access transistors is performed via the first primary control line (access transistors 166 and 168).
Regarding claim 6, Kumar further teaches the method according to claim 1, wherein the application of the control signal including applying the control signal to both access transistors via the primary control line (WL applies signal to both transistors 166 and 168).
Regarding claim 7, Kodama and Kumar further teaches the method according to claim 1, wherein the application of the control signal to the control terminal of the at least one of the two access transistors in such a way that the load path of the at least one access transistor is at least partially electrically conductive when the load path is in the first-resistance state includes: applying a control voltage to the control terminal of the at least one of the two access transistors, wherein the control voltage is less than or equal to a threshold voltage of the at least one access transistor (Kodama, see Fig. 3 and Fig. 11).
Regarding claim 8, Kodama and Kumar further teaches the method according to claim 1, wherein the memory device includes a plurality of memory units, wherein the method includes: applying the control signal to a relevant control terminal of at least one of the two access transistors of the plurality of memory units in such a way that a load path of the relevant at least one access transistor of the plurality of memory units is at least partially electrically conductive with respect to a high-resistance state of the load path of the at least one access transistor, the determination of the first variable characterizing a sum of currents flowing through the respective load paths of the at least one access transistor of the plurality of memory units (Kodama, see Fig. 3 and Fig. 11).
Regarding claim 9, Kumar further teaches the method according to claim 8, wherein the application is performed using at least the first primary control line (Fig. 1B, word line WL).
Regarding claim 10, Kumar further teaches the method according to claim 1, wherein the first variable is detected with a current-based, analog/digital converter device (¶0095, performs current based summing).
Regarding claim 11, Kumar further teaches the method according to claim 10, wherein the analog/digital converter device is a differential analog/digital converter device (Fig. 2B or Fig. 2C, uses differential amplifier).
Regarding claim 12, Kumar further teaches the method according to claim 1, further comprising at least one of the following elements: a) at least a temporary operation of the memory device in a first digital operating mode in which a control voltage greater than a threshold voltage of the at least one of the two access transistors is used for the application to the control terminal of the at least one of the two access transistors; b) at least a temporary operation of the memory device in a second analog operating mode, in which a control voltage less than or equal to the threshold voltage of the at least one of the two access transistors is used for the application to the control terminal of the at least one of the two access transistors (Fig. 1B, the word line WL uses a higher voltage than a threshold voltage of the access transistors 166 or 168 in order to turn the transistors to access the memory cells).
Regarding claims 13-20, the claims have similar limitations as claims 1-12 except the claims are written in a different format. Therefore, the claims are rejected under the same grounds of rejection.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824