DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-20, in the reply filed on February 27, 2026 is acknowledged. Therefore, claims 1-20 are presented for examination.
Claim Objections
Claims 3 and 15 are objected to because of the following informalities:
In claims 3 and 15, the phrase “whether the substrate includes a solder mask, and wherein…” should be amended with “wherein the substrate includes a solder mask, and wherein…” to clarify the scope of the claim and avoid indefiniteness.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over by Lin et al. (US 2012/0018884, hereinafter Lin) in view of Cyr (US 2016/0240227).
Regarding claim 1, Lin discloses for a semiconductor device assembly, comprising that a substrate (substrate 10, Fig. 5);
a plurality of first electrical contacts (a plurality of first connecting points 14, Fig. 5) disposed on the substrate (10, Fig. 5);
a load switch (chip 30, Fig. 5) coupled to the substrate (10, Fig. 5) and including a first outer surface (bottom surface of the chip 30, Fig. 5) facing the substrate (10, Fig. 5) and an opposing second outer surface (top surface of the chip 30, Fig. 5) facing away from the substrate (10, Fig. 5); Examiner notes that Applicants do not specifically claim the structural features of the recited “a load switch” nor the functional characteristics of the load switch or the nature of the “load”, therefore, the term “load switch” may include any switching circuitry configured to control delivery of electrical signal or power to a load within the semiconductor device assembly,
wherein the load switch (30, Fig. 5) includes a plurality of second electrical contacts (a plurality of pads 33, Fig. 5) disposed on the second outer surface (top surface of 30, Fig. 5); and
a plurality of wire bonds (a plurality of wires 40, Fig. 5) electrically coupling the load switch (30, Fig. 5) to the substrate (10, Fig. 5),
wherein each wire bond (each 40, Fig. 5), of the plurality of wire bonds (plurality of 40, Fig. 5), electrically couples a corresponding first electrical contact (14, Fig. 5), of the plurality of first electrical contacts (plurality of 14, Fig. 5), to a corresponding second electrical contact (corresponding 33, Fig. 5), of the plurality of second electrical contacts (plurality of 33, Fig. 5).
Lin does not explicitly disclose a load switch.
However, Cyr discloses for a semiconductor device package that the semiconductor device assembly 210 (Fig. 2A) includes a switch circuit 234 electrically coupled to a support substrate 212, which corresponds to the substrate in the claimed invention, and Cyr further discloses that “switch circuit 234 configured to receive a switch signal S1 having a predetermined signal value (e.g., a predetermined voltage level” (emphasis added, [0015]), “the switch circuit 234 can be configured to toggle a memory device package into mirror mode when the switch signal S1 is low and into normal mode when the switch signal S1 is high” (emphasis added, [0015]), and “the switch circuit 234 can program a memory device package into either a normal mode or a mirrored mode” ([0018]). Thus, Cyr teaches the switch circuit 234 responds to electrical signal (i.e., voltage) to control operation of components within the semiconductor device package. In view of Cyr, one of ordinary skill in the semiconductor packaging art would have recognized that the switch circuit 234 constitutes switching circuitry capable of selectively controlling electrical operation within the package, which can correspond to the load switch in the claimed invention, and it is obvious to incorporate such switching circuitry into the semiconductor package of Lin, for example, by configuring the chip 30 of Lin to include or implement the switch circuit functionality disclosed by Cyr, in order to control or manage operation and power distribution within the semiconductor device package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Lin to include switching circuitry as disclosed by Cyr, in order to provide a load switch for controlling operation with the package.
Regarding claim 2, Lin further discloses for the semiconductor device assembly of claim 1 that an adhesive layer (adhesive layer 20, Fig. 5) coupling the load switch (30, Fig. 5) to the substrate (10, Fig. 5).
Regarding claim 3, Lin further discloses for the semiconductor device assembly of claim 2 that whether (see Claim Objections) the substrate (10, Fig. 5) includes a solder mask (second encapsulant 60, Fig. 5), and wherein the adhesive layer (20, Fig. 5) couples the load switch (30, Fig. 5) to the solder mask (60, Fig. 5), because Applicants do not specifically claim what the solder mask is made of and/or what structural features the solder mask have, and Applicants originally disclosed that the claimed solder mask 408 is disposed on the substrate 404 and encapsulates the first electrical contacts 406 (Fig. 4 of the present application), the second encapsulant 60 by Lin is disposed on the substrate 10 and encapsulates the chip 30 and the first connecting points 14 (Fig. 5), which corresponds to the first electrical contacts in the claimed invention, therefore, the second encapsulant 60 by Lin corresponds to the solder mask in the claimed invention.
Regarding claim 5, Cyr further discloses that the load switch (switch circuit 234, Fig. 2A) is internal to a memory package (first memory device package 214a, Fig. 2A).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2012/0018884, hereinafter Lin) in view of Cyr (US 2016/0240227) as applied to claim 1, and further in view of Chen et al. (US 2018/0286847, hereinafter Chen). The teachings of Lin in view of Cyr are discussed above.
Regarding claim 4, Lin in view of Cyr does not explicitly disclose that the adhesive layer includes a die attach film.
However, Chen discloses for a semiconductor device package that the integrated circuit die 102 is coupled to the carrier 101 in the integrated circuit die mounting region 104 (Fig. 1) “using an adhesive or a die attach film (DAF)…” (emphasis added, [0076]), therefore, one of ordinary skill in the semiconductor packaging art would have recognized that the die attach film by Chen can be used as the adhesive layer in the semiconductor package of Lin, because die attach films are well known and widely used to provide enhanced adhesion, electrical insulation, and mechanical stability in semiconductor packaging.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that die attach films can be used to couple the semiconductor die onto a substrate, as disclosed by Chen, in order to improve adhesion, electrical insulation, and mechanical stability in semiconductor packaging.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over by Lin et al. (US 2012/0018884, hereinafter Lin) in view of Cyr (US 2016/0240227) as applied to claim 1, and further in view of Ide (US 2020/0096558). The teachings of Lin in view of Cyr are discussed above.
Regarding claim 6, Lin differs from the claimed invention by not showing that a memory package electrically coupled to the substrate, wherein the load switch is coupled to the substrate external to the memory package.
However, Cyr discloses that the first memory device package 214a is electrically coupled to the support substrate 212 (Fig. 3A), and Cyr further discloses that the switch circuit 234, which corresponds to the load switch in the claimed invention, is coupled to the support substrate 212.
Further regarding claim 6, Lin in view of Cyr differs from the claimed invention by not showing that the load switch is coupled to the substrate external to the memory package.
However, Ide discloses for a semiconductor memory device that the memory device 400 (Fig. 4) includes a pair of memory dies 402a/402b and the interface die 404 (IF die), and the IF die includes the switch circuit 430, which may correspond to the load switch in the claimed invention, which is present external to the memory dies 402a/402b (Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor memory package can include memory die and the switching circuit coupled to the substrate, and the switching circuit can be implemented separately with the memory die, as disclosed by Ide, for an alternative packaging design choice, in order to improve the memory device performance.
Claims 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over by Irsigler et al. (US 2008/0099925, hereinafter Irsigler) in view of Cyr (US 2016/0240227).
Regarding claim 7, Irsigler discloses for a semiconductor device assembly, comprising that
a substrate (second component 120, Fig. 4D), because “the second component 120 may comprise a substrate or another die” (emphasis added, [0035]), therefore, the second component 120 by Irsigler corresponds to the substrate in the claimed invention;
a plurality of first electrical contacts (a plurality of metallization pads 122, Fig. 4D) disposed on the substrate (120, Fig. 4D);
a load switch (semiconductor die 20, Fig. 4D) coupled to the substrate (120, Fig. 4D) and including a plurality of second electrical contacts (a plurality of pads 22, Fig. 4D); and
a plurality of pillar interconnects (a plurality of metal pillars 30, Fig. 4D) electrically coupling the load switch (20, Fig. 4D) to the substrate (120, Fig. 4D),
wherein each pillar interconnect (30, Fig. 4D), of the plurality of pillar interconnects (plurality of 30, Fig. 4D), electrically couples a corresponding first electrical contact (122, Fig. 4D), of the plurality of first electrical contacts (plurality of 122, Fig. 4D), to a corresponding second electrical contact (22, Fig. 4D), of the plurality of second electrical contacts (plurality of 22, Fig. 4D).
Irsigler does not explicitly disclose a load switch.
However, Cyr discloses for a semiconductor device package that the semiconductor device assembly 210 (Fig. 2A) includes a switch circuit 234 electrically coupled to a support substrate 212, which corresponds to the substrate in the claimed invention, and Cyr further discloses that “switch circuit 234 configured to receive a switch signal S1 having a predetermined signal value (e.g., a predetermined voltage level” (emphasis added, [0015]), “the switch circuit 234 can be configured to toggle a memory device package into mirror mode when the switch signal S1 is low and into normal mode when the switch signal S1 is high” (emphasis added, [0015]), “the switch circuit 234 can program a memory device package into either a normal mode or a mirrored mode” ([0018]). Thus, Cyr teaches the switch circuit 234 responds to electrical signal (i.e., voltage) to control operation of components within the semiconductor device package. In view of Cyr, one of ordinary skill in the semiconductor packaging art would have recognized that the switch circuit 234 constitutes switching circuitry capable of selectively controlling electrical operation within the package, which can correspond to the load switch in the claimed invention, and it is obvious to incorporate such switching circuitry into the semiconductor package of Irsigler, for example, by configuring the semiconductor die 20 of Irsigler to include or implement the switch circuit functionality disclosed by Cyr, in order to control or manage operation and power distribution within the semiconductor device package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Irsigler to include switching circuitry as disclosed by Cyr, in order to provide a load switch for controlling operation with the package.
Regarding claim 8, Irsigler further discloses for the semiconductor device assembly of claim 7 that solder paste (solder covered pads 132, Fig. 4D) coupling the plurality of pillar interconnects (30, Fig. 4D) to the plurality of first electrical contacts (122, Fig. 4D).
Regarding claim 9, Irsigler further discloses for the semiconductor device assembly of claim 7 that a filler material (encapsulant 80, Fig. 4D) disposed between the load switch (20, Fig. 4D) and the substrate (120, Fig. 4D) and encapsulating the plurality of pillar interconnects (30, Fig. 4D).
Regarding claim 10, Irsigler further discloses for the semiconductor device assembly of claim 9 that the filler material (80, Fig. 4D) includes at least one of a mold compound, a mold underfill, or a capillary underfill, because “other alternatives steps may include forming an undermold between the die and the second component. Another alternative step may include forming a liquid underfill between the die and the second component” (emphasis added, [0035], Figs. 10A-C, 11).
Regarding claim 11, Cyr further discloses that the load switch (switch circuit 234, Fig. 2A) is internal to a memory package (first memory device package 214a, Fig. 2A).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over by Irsigler et al. (US 2008/0099925, hereinafter Irsigler) in view of Cyr (US 2016/0240227) as applied to claim 7, and further in view of Ide (US 2020/0096558). The teachings of Irsigler in view of Cyr are discussed above.
Regarding claim 12, Irsigler differs from the claimed invention by not showing that a memory package electrically coupled to the substrate, wherein the load switch is coupled to the substrate external to the memory package.
However, Cyr discloses that the first memory device package 214a is electrically coupled to the support substrate 212 (Fig. 3A), and Cyr further discloses that the switch circuit 234, which corresponds to the load switch in the claimed invention, is electrically coupled to the support substrate 212.
Further regarding claim 12, Irsigler in view of Cyr differs from the claimed invention by not showing that the load switch is coupled to the substrate external to the memory package.
However, Ide discloses for a semiconductor memory device that the memory device 400 (Fig. 4) includes a pair of memory dies 402a/402b and the interface die 404 (IF die), and the IF die includes the switch circuit 430, which may correspond to the load switch in the claimed invention, which is present external to the memory dies 402a/402b (Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor memory package can include memory die and the switching circuit coupled to the substrate, and the switching circuit can be implemented separately with the memory die, as disclosed by Ide, for an alternative packaging design choice, in order to improve the memory device performance.
Claims 13-14, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0286847, hereinafter Chen) in view of Cyr (US 2016/0240227).
Regarding claim 13, Chen discloses for a memory device comprising that
a substrate (substrate 154, Fig. 15) including a plurality of first electrical contacts (a plurality of contact pads on the substrate 154, Fig. 15) and a plurality of second electrical contacts (a plurality of contact pads on the dies 156, Fig. 15);
one or more memory dies (one of the dies 156, Fig. 15) electrically coupled to the substrate (154, Fig. 15) via the plurality of first electrical contacts (plurality of contact pads on the substrate 154, Fig. 15), because “the dies 156 may comprise dynamic random access memory (DRAM) devices in some embodiments” (emphasis added, [0070]), therefore, the die 156 by Chen corresponds to the memory die in the claimed invention;
a load switch (another die 156, Fig. 15) electrically coupled to the substrate (154, Fig. 15) via at least one of a plurality of wire bonds (a plurality of wire bonds 152, Fig. 15) or a plurality of pillar interconnects; and
at least one of a casing (molding material 148, Fig. 15) surrounding the one or more memory dies (one of the die 156, Fig. 15) and the load switch (another die 156, Fig. 15), because Applicants do not specifically claim what the casing is made of and/or what material’s composition the casing has, the molding material 148 by Chen covers an entire upper portion of the semiconductor package, therefore, the molding material 148 can correspond to the casing in the claimed invention or a mold compound (molding material 148, Fig. 15) encapsulating the at least one of the plurality of wire bonds (152, Fig. 15) or the plurality of pillar interconnects.
Chen does not explicitly disclose a load switch.
However, Cyr discloses for a semiconductor device package that the semiconductor device assembly 210 (Fig. 2A) includes a switch circuit 234 electrically coupled to a support substrate 212, which corresponds to the substrate in the claimed invention, and Cyr further discloses that “switch circuit 234 configured to receive a switch signal S1 having a predetermined signal value (e.g., a predetermined voltage level” (emphasis added, [0015]), “the switch circuit 234 can be configured to toggle a memory device package into mirror mode when the switch signal S1 is low and into normal mode when the switch signal S1 is high” (emphasis added, [0015]), “the switch circuit 234 can program a memory device package into either a normal mode or a mirrored mode” ([0018]). Thus, Cyr teaches the switch circuit 234 responds to electrical signal (i.e., voltage) to control operation of components within the semiconductor device package. In view of Cyr, one of ordinary skill in the semiconductor packaging art would have recognized that the switch circuit 234 constitutes switching circuitry capable of selectively controlling electrical operation within the package, which can correspond to the load switch in the claimed invention, and it is obvious to incorporate such switching circuitry into the semiconductor package of Chen, for example, by configuring one of the dies 156 of Chen to include or implement the switch circuit functionality disclosed by Cyr, in order to control or manage operation and power distribution within the semiconductor device package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of Chen to include switching circuitry as disclosed by Cyr, in order to provide a load switch for controlling operation with the package.
Regarding claim 14, Chen further discloses for the memory device of claim 13 that the load switch (one of the die 156, Fig. 15) is electrically coupled to the substrate (154, Fig. 15) via the plurality of wire bonds (152, Fig. 15), wherein the memory device (packaged semiconductor device 150, Fig. 15) further comprises an adhesive layer coupling the load switch (one of the die 156, Fig. 15) to the substrate (154, Fig. 15), because Chen further discloses “the integrated circuit die 102 is coupled to the carrier 101 in the integrated circuit die mounting region 104 as shown in FIG. 1 using an adhesive or die attach film (DAF)…” (emphasis added, [0076]), therefore, it is obvious to one of ordinary skill in the semiconductor packaging art that the adhesive or die attach film (DAF) would be used to couple the die 156 to the substrate 154 (Fig. 15).
Regarding claim 16, Chen further discloses for the memory device of claim 14 that the adhesive layer includes a die attach film (DAF, [0076]).
Regarding claim 20, Chen further discloses for the memory device of claim 13 that a controller (integrated circuit die 102, Fig. 15) operatively connected to the one or more memory dies (156, Fig. 15), wherein the at least one of the casing or the mold compound (molding material 116, Fig. 15) encloses the controller (102, Fig. 15), because “the integrated circuit die 102 may comprise a logic chip, a memory chip, a processor, an application specific device, or a chip having other functions, as examples” ([0075]), therefore, the integrated circuit die 102 by Chen can correspond to the controller in the claimed invention and it is coupled to the packaged semiconductor device 150 (i.e., the dies 156) via the interconnect structure 120 (Fig. 15).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0286847, hereinafter Chen) in view of Cyr (US 2016/0240227), as applied to claim 13, and further in view of Lin et al. (US 2012/0018884, hereinafter Lin). The teachings of Chen in view of Cyr are discussed above.
Regarding claim 15, Chen in view of Cyr differs from the claimed invention by not showing that whether (see Claim Objections) the substrate includes a solder mask, and wherein the adhesive layer couples the load switch to the solder mask.
However, Lin discloses that the substrate (10, Fig. 5) includes the first encapsulant 50 encapsulating the chip 30 (Fig. 5), and therefore, the first encapsulant 50 can correspond to the casing in the claimed invention, and further discloses that a solder mask (second encapsulant 60, Fig. 5) and the adhesive layer (20, Fig. 5) couples the load switch (30, Fig. 5) to the solder mask (60, Fig. 5), because Applicants do not specifically claim what the solder mask is made of and/or what structural features the solder mask have, and Applicants originally disclosed that the claimed solder mask 408 is disposed on the substrate 404 and encapsulates the first electrical contacts 406 (Fig. 4 of the present application), the second encapsulant 60 by Lin is disposed on the substrate 10, and encapsulates the chip 30 and the first connecting points 14 (Fig. 5), which corresponds to the first electrical contacts in the claimed invention, therefore, the second encapsulant 60 by Lin can correspond to the solder mask in the claimed invention.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the solder mask or other suitable protection layer, such as encapsulation layer disclosed by Lin, in order to protect the electrical contacts from environmental and physical damage, thereby improving the reliability and durability of the semiconductor device package.
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2018/0286847, hereinafter Chen) in view of Cyr (US 2016/0240227), as applied to claim 13, and further in view of Irsigler et al. (US 2008/0099925, hereinafter Irsigler). The teachings of Chen in view of Cyr are discussed above.
Regarding claim 17, Chen in view of Cyr differs from the claimed invention by not showing that the load switch is electrically coupled to the substrate via the plurality of pillar interconnects, and wherein the memory device further comprises solder paste coupling the plurality of pillar interconnects to the plurality of first electrical contacts.
However, Irsingler discloses that the die 20, which may correspond to the load switch or memory device in the claimed invention, is electrically coupled to the substrate (second component 120, Fig. 4D) via the plurality of pillar interconnects (plurality of metal pillars 30, Fig. 4D), and the solder covered pads 132 are coupled with the plurality of metal pillars 30 to electrically connect the metal pillars to the plurality of metallization pads 122 (Fig. 4D), therefore, the solder covered pads 132 corresponds to the solder paste in the claimed invention, and the metallization pads 122 corresponds to the first electrical contacts in the claimed invention; therefore, one of ordinary skill in the semiconductor packaging art would have recognized that the semiconductor dies of Chen could be electrically coupled to the substrate using pillar-type interconnects and/or solder material as taught by Irsigler, because these features are well known for providing reliable electrical connection for the semiconductor device package.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide pillar-type interconnects and solder material to electrically couple semiconductor dies to the substrate contacts, as disclosed by Irsigler, in order to improve electrical connection performance in the semiconductor package.
Regarding claim 18, Irsigler further discloses that a filler material (encapsulant 80, Fig. 4D) disposed between the load switch (20, Fig. 4D) and the substrate (120, Fig. 4D) and encapsulating the plurality of pillar interconnects (30, Fig. 4D).
Regarding claim 19, Irsigler further discloses that the filler material (80, Fig. 4D) includes at least one of a mold compound, a mold underfill, or a capillary underfill, because “other alternatives steps may include forming an undermold between the die and the second component. Another alternative step may include forming a liquid underfill between the die and the second component” (emphasis added, [0035], Figs. 10A-C, 11).
Conclusion
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/WOO K LEE/Examiner, Art Unit 2815