DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant’s election without traverse of Group I, Species I, Embodiment 1 (boron), and Claims 1-3 and 9-19 in the reply filed on August 18, 2025 is acknowledged. Thus, Claim 7 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention. Election was made without traverse in the reply filed on August 18, 2025.
Specification
The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 9-17 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent Application Publication No. 2019/0312052 A1 to Lee et al. (“Lee”). As to claim 1, Lee further discloses wherein the conductive rail (154) is a T-shaped rail (FIG. 18A) of a conductive material, the T-shaped rail (FIG. 18A) of the conductive material defining an outer sidewall of the individual ones of the at least some vertically neighboring conductive tiers (GE) (See Fig. 13, Fig. 18, ¶ 0079).
As to claim 2, Lee further discloses wherein, for the at least some vertically neighboring conductive tiers (GE), the conductive tiers (GE) individually have a planar upper surface and a planar lower surface along the width of the interior conductive region (154) (See Fig. 3, Fig. 18).
As to claim 3, Lee further discloses wherein at least a portion of an upper surface of each of the conductive rails (154) is coplanar with an upper surface of the interior region (152, 154) from which the conductive rails (154) extend (See Fig. 3, Fig. 18).
As to claim 9, Lee discloses an electronic apparatus, comprising: a stack structure divided into blocks (ST) and comprising vertically repeated tier groups (GE, ILD), the tier groups (GE, ILD) individually comprising at least one conductive tier (GE) and at least one insulative tier (ILD); pillars (VS) extending vertically through the stack structure, the pillars (VS) individually comprising a channel region (LSP, USP); and at least one fill material (ESS) extending between the blocks (ST), a least some vertically neighboring conductive tiers (GE), of the at least one conductive tier (GE) of the stack structure, individually comprising: a conductive rail (154) extending from an end of an interior conductive region (154), the conductive rail (154) being adjacent the at least one fill material (ESS), the conductive rail (154) of one of the vertically neighboring conductive tiers (GE) being spaced from the conductive rail (154) of another of the vertically neighboring conductive tiers (GE) by an air gap (AG) (See Fig. 1, Fig. 2, Fig. 13, Fig. 18, ¶ 0021, ¶ 0023, ¶ 0026, ¶ 0029-¶ 0031, ¶ 0038-¶ 0044, ¶ 0079, ¶ 0081, ¶ 0087).
As to claim 10, Lee further discloses wherein the tier groups (GE, ILD) individually consist of one of the conductive tiers (GE) and one of the insulative tiers (ILD) (See Fig. 2, ¶ 0023).
As to claim 11, Lee further discloses wherein the channel region (LSP, USP) has a hollow structure (¶ 0030), the pillars (VS) individually further comprising at least one other fill material (TIL) interior to the hollow structure (¶ 0030) (See Fig. 18, ¶ 0030, ¶ 0031).
As to claim 12, Lee further discloses wherein upper and lower surfaces of the conductive rail (154) are at least partially coplanar with the planar upper surface and the planar lower surface, respectively, of the interior conductive region (154) from the end of which the conductive rail (154) extends (See Fig. 3, Fig. 18).
As to claim 13, Lee discloses a memory device, comprising: a stack comprising insulative tiers (ILD) and conductive tiers (GE) arranged in vertically repeated tier groups, the tier groups individually comprising at least one of the conductive tiers (GE) and at least one of the insulative tiers (ILD); fill materials (ESS) separating the stack into blocks (ST); and pillars (VS) extending through the stack, the pillars (VS) individually comprising a channel region (LSP, USP), at least some of the conductive tiers (GE) individually comprising: an interior region (152, 154) comprising at least one conductive material; and conductive rails (154) extending from ends of the interior region (152, 154), the conductive rails (154) extending horizontally beyond sidewalls of vertically neighboring insulative tiers (ILD) of the insulative tiers (LD) of the stack, the fill materials (ESS) partially conforming to sidewalls of the stack and defining air gaps (AG) between vertically neighboring pairs of the conductive rails (154) (See Fig. 1, Fig. 2, Fig. 13, Fig. 18, ¶ 0021, ¶ 0023, ¶ 0026, ¶ 0029-¶ 0031, ¶ 0038-¶ 0044, ¶ 0079, ¶ 0081, ¶ 0087).
As to claim 14, Lee further discloses wherein the interior region (154) is directly vertically between the vertically neighboring insulative tiers (ILD) of the insulative tiers (ILD) of the stack (See Fig. 2, Fig. 3, Fig. 18).
As to claim 15, Lee further discloses wherein the at least one conductive material of the interior region (152, 154) comprises a conductive material disposed on another conductive material (See Fig. 3, ¶ 0038).
As to claim 16, Lee further discloses wherein the conductive rails (154) and the conductive material of the interior region (152, 154) have substantially a same composition (See Fig. 3, ¶ 0038).
As to claim 17, Lee further discloses wherein the conductive rails (154) extend partially along the sidewalls of the vertically neighboring insulative tiers (ILD) (See Fig. 2, Fig. 3, Fig. 18).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2019/0312052 A1 to Lee et al. (“Lee”) as applied to claim 13 above, and further in view of U.S. Patent Application Publication No. 2017/0352671 A1 to Kato et al. (“Kato”). The teaching of Lee has been discussed above. As to claim 18, Lee in view of Kato discloses further comprising a polymer (66) on the sidewalls of the vertically neighboring insulative tiers (ILD/45) (See Lee Fig. 3 and Kato Fig. 15, Fig. 16, ¶ 0059, ¶ 0060, ¶ 0061, ¶ 0068, ¶ 0069) such that the polymer prevents an unwanted metal from depositing to reduce further patterning.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2019/0312052 A1 to Lee et al. (“Lee”) as applied to claim 13 above, and further in view of U.S. Patent Application Publication No. 2010/0038784 A1 to Edelstein et al. (“Edelstein”). The teaching of Lee has been discussed above. As to claim 19, Lee in view of Edelstein discloses further comprising boron (B) between the ends of the interior region (152, 154/24, 26, 28) and the conductive rails (154/28) extending from the ends (See Lee Fig. 3, ¶ 0038 and Edelstein Fig. 7, Fig. 8, Fig. 9, ¶ 0001, ¶ 0004, ¶ 0006, ¶ 0008, ¶ 0024-¶ 0031) such that a better diffusion barrier is formed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815