Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/7/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 19 is objected to because of the following informalities: “a first direction” in line 3. For the sake of compact prosecution, claim 19 is interpreted in the instant Office action as follows: “a first direction” is found to be a typographical error and is believed to be equivalent to “the first direction” based on antecedence for this term in claim 15, line 5; however, no actual change to the claim language has been applied during examination of the instant set of claims. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 9-11, 13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Huang (US 20210305145 A1).
Regarding claim 1, Huang discloses a semiconductor package (Fig. 10), comprising:
a package substrate (200);
an interposer (140) disposed on the package substrate (on in the Z direction, See annotated figure for direction designation); and
a first semiconductor chip (110) disposed on the interposer (on in the Z direction),
wherein the interposer includes:
a first semiconductor substrate (141, See annotated figure); and
a first dielectric layer (a layer of 144; [0019]: one of the plural “passivation layers”) disposed on the first semiconductor substrate (on in the Z direction),
wherein the first dielectric layer includes a first scribe lane region (See annotated figure for dashed reference lines. Note: this region is interpreted here consistent with at least Fig. 2: region SR of Applicant’s disclosure.),
wherein the first scribe lane region is below the first semiconductor chip (See annotated figure for “below” designation) along a first direction (the Z direction is being designated as the first direction. Note: the region is below with respect to height, without any requirement for overlap in this direction) that is perpendicular to a top surface of the first semiconductor substrate (the Z direction is perpendicular to surface 141t), and
wherein the first scribe lane region is spaced apart from a lateral surface of the interposer (lateral surface at PL, See annotated figure. Note: the region designated by the dashed reference lines as a portion of 140 that isn’t including PL).
Illustrated below is a marked and annotated figure of Fig. 10 of Huang.
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Regarding claim 2, Huang discloses the semiconductor package of claim 1 (Fig. 10), wherein the first scribe lane region has a tetragonal ring shape (See annotated Fig. 9, a top-down view of Fig. 10) having an inner edge (See annotated figure, a region edge, without any particular structural definition) and an outer edge (See annotated figure, a region edge, without any particular structural definition), and wherein the inner edge and the outer edge each overlap the first semiconductor chip (overlap in at least a diagonal direction different from the Z direction).
Illustrated below is a marked and annotated figure of Fig. 9 of Huang.
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Regarding claim 3, Huang discloses the semiconductor package of claim 1 (Fig. 10), wherein the first scribe lane region has a tetragonal ring shape (See annotated Fig. 9, a top-down view of Fig. 10) having an inner edge (See annotated figure, a region edge, without any particular structural definition) and an outer edge (See annotated figure, a region edge, without any particular structural definition), and wherein the inner edge overlaps the first semiconductor chip (overlap in at least a diagonal direction different from the Z direction), and the outer edge is exposed by the first semiconductor chip (“exposed” because the 1st chip doesn’t overlap this edge in the Z direction).
Regarding claim 4, Huang discloses the semiconductor package of claim 1 (Fig. 10), wherein the first dielectric layer further includes a dummy region (See annotated figure. Note: this region is interpreted here consistent with at least Fig. 2: region DR of Applicant’s disclosure.) that at least partially surrounds the first scribe lane region (fully surrounds in the top-down view of Fig. 9), and wherein at least a portion of the dummy region is positioned in a diagonal direction with respect to the first semiconductor chip (diagonal direction different from the Z direction).
Regarding independent claim 9, Huang discloses a semiconductor package (Fig. 10), comprising:
a package substrate (200);
an interposer disposed on the package substrate (140); and
a semiconductor chip (110) disposed on the interposer (on in the Z direction), wherein the interposer includes:
a first semiconductor substrate (141, See annotated figure); and a
first dielectric layer (a layer of 144; [0019]: one of the plural “passivation layers”) disposed on the first semiconductor substrate (on in the Z direction),
wherein the first dielectric layer includes:
a wiring region (See annotated figure for dashed reference lines. Note: this region is interpreted here consistent with at least Fig. 2: region AR of Applicant’s disclosure.);
a scribe lane region (See annotated figure for dashed reference lines. Note: this region is interpreted here consistent with at least Fig. 2: region SR of Applicant’s disclosure.) that at least partially surrounds the wiring region (See annotated Fig. 9, a top-down view of Fig. 10); and
a dummy region (See annotated figure. Note: this region is interpreted here consistent with at least Fig. 2: region DR of Applicant’s disclosure.) that at least partially surrounds the scribe lane region (See annotated Fig. 9, a top-down view of Fig. 10), wherein at least a portion of the dummy region at least partially surrounds the semiconductor chip (Fig. 10 shows at least partial surrounding at a different Z height).
Regarding claim 10, Huang discloses the semiconductor package of claim 9 (Fig. 10), wherein a lateral surface of the first semiconductor substrate (surface of 141 at PL) is coplanar (coplanar in the Z direction) with a lateral surface of the first dielectric layer (surface of 144 at PL), and wherein the lateral surface of the first dielectric layer is an outer edge of the dummy region (See annotated figure for edge designation).
Regarding claim 11, Huang discloses the semiconductor package of claim 9 (Fig. 10), further comprising an underfill pattern (150) disposed between the semiconductor chip and the interposer (between in the Z direction), wherein the underfill pattern covers the dummy region (indirectly covers in a diagonal direction).
Regarding claim 13, Huang discloses the semiconductor package of claim 9 (Fig. 10), wherein the semiconductor chip is a logic chip or a memory chip ([0014]: “a logic die”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Huang.
Regarding claim 8, Huang discloses the semiconductor package of claim 1 (Fig. 10), wherein the first semiconductor chip includes:
a second semiconductor substrate (112); and
a second dielectric layer (116; [0015]: “passivation layer”) disposed on the second semiconductor substrate (on in the Z direction),
wherein the second dielectric layer includes a second scribe lane region (See annotated figure),
wherein the first scribe lane region has a first width in a second direction (See annotated figure for direction designation) parallel to the top surface of the first semiconductor substrate,
wherein the second scribe lane region has a second width in the second direction (See annotated figure for direction designation), and
wherein the first width is greater than the second width (See additional remarks below. There are no specific structural boundaries for either the first or second scribe lane regions in the reference or the claim. Thus, these regions may be arbitrarily chosen within scope of Huang’s disclosure to include the claimed “greater than” configuration).
Further regarding the scribe lane region relative sizes (i.e., “wherein the first width is greater than the second width”), Huang illustrates the claimed scribe regions but is silent regarding their particular width measurement positions (i.e., dimensions). However, the claim as written reasonably encompasses a plurality of interpretations of these regions, without requiring any particular reconfiguration of the package. Thus, Huang appears to disclose regions that may be variably defined consistent with the claim. Therefore, the claimed relative dimensions of the regions would have been prima facie obvious to one of ordinary skill in the art before the effective filing date because they are not patentably distinct from the package disclosed by Huang. MPEP 2111; MPEP 2144.04 (IV)(A).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 4 above, and further in view of Choi (US 20210175133 A1).
Regarding claim 5, Huang discloses the semiconductor package of claim 4 (Fig. 10), and teaches the interposer, however fails to teach an inspection pattern. Thus, Huang fails to teach “wherein the interposer further includes an inspection pattern disposed on the first scribe lane region, and wherein the inspection pattern includes a test element group and/or a wafer alignment key”.
Choi discloses an inspection pattern (Fig. 33: 49A) disposed on the first scribe lane region (SL11), and wherein the inspection pattern includes a test element group ([0037]: “a test element group”) and/or a wafer alignment key.
Modifying the first scribe lane region of Huang by including inspection pattern of Choi would arrive at the claimed interposer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each case the scribe lane region includes a semiconductor substrate (Huang: substrate 141, [0018]: “a semiconductor material”: Choi: substrate 21, [0039]: “a semiconductor substrate”). Choi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the inspection pattern in that it would enable early detection of manufacturing defects ([0037]: “may be electrically tested for determining whether elements of the chip regions CH are suitably formed on the wafer in a manufacturing process”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed inspection pattern because it would enable early detection of manufacturing defects. MPEP 2143 (I)(G).
Illustrated below is Fig. 33 of Choi.
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Regarding claim 6, Huang in view of Choi discloses the semiconductor package of claim 5 (Choi: Fig. 33), further comprising a passivation layer (35A) that covers the first dielectric layer (31), wherein the inspection pattern includes an exposure pattern (45), and wherein the exposure pattern is exposed by the passivation layer (partially exposed).
Regarding claim 7, Huang in view of Choi discloses the semiconductor package of claim 6 (Choi: Fig. 1), wherein the passivation layer covers the first scribe lane region (partially covers) and exposes the dummy region (SLC1, corresponds to dummy region of Huang).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 9 above, and further in view of Choi.
Regarding claim 12, Huang discloses the semiconductor package of claim 9 (Fig. 10), and teaches the interposer, however, fails to teach an inspection pattern. Thus, Huang fails to teach “wherein the interposer further includes an inspection pattern disposed on the scribe lane region, wherein the inspection pattern includes a test element group and/or a wafer alignment key, and wherein the inspection pattern vertically overlaps the semiconductor chip”.
Choi discloses an inspection pattern (Fig. 33: 49A) disposed on the scribe lane region (SL11), wherein the inspection pattern includes a test element group ([0037]: “a test element group”) and/or a wafer alignment key, and wherein the inspection pattern vertically overlaps the semiconductor chip (vertical is designated here as a diagonal direction including at least some component direction perpendicular to substrate 21).
Modifying the scribe lane region of Huang by including inspection pattern of Choi would arrive at the claimed interposer configuration and the spatial configuration with the semiconductor chip because in Huang, the semiconductor chip vertically overlaps the semiconductor chip (vertical is designated here as a diagonal direction including at least some component direction perpendicular to 140). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each case the scribe lane region includes a semiconductor substrate (Huang: substrate 141, [0018]: “a semiconductor material”: Choi: substrate 21, [0039]: “a semiconductor substrate”). Choi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the inspection pattern in that it would enable early detection of manufacturing defects ([0037]: “may be electrically tested for determining whether elements of the chip regions CH are suitably formed on the wafer in a manufacturing process”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed inspection pattern because it would enable early detection of manufacturing defects. MPEP 2143 (I)(G).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 9 above, and further in view of Yang (US 20220157777 A1).
Regarding claim 14, Huang discloses the semiconductor package of claim 9 (Fig. 10),
wherein the semiconductor chip is a dummy chip, and wherein the dummy chip includes:
a second semiconductor substrate (112; [0016]: “semiconductor materials”); and
a metal pad (114; [0016]: “metal pads”) in direct contact with the second semiconductor substrate (direct contact is illustrated).
Huang fails to teach “the semiconductor chip is a dummy chip”.
Yu discloses a semiconductor package (Fig. 1D) with a semiconductor chip (40), wherein the semiconductor chip is a dummy chip ([0042]: “dummy dies”), and wherein the dummy chip includes: a second semiconductor substrate ([0035]: “silicon”); and a metal pad (this “pad” is a required interface for [0042]: “the dummy dies 40 can be reflowed”) in direct contact with the second semiconductor substrate.
Modifying the semiconductor package of Huang, by including a semiconductor chip (structurally of Huang) that is a dummy chip (according to the teachings of Yu) would arrive at the claimed chip configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Yu teaches a dummy chip may be made from a repurposed chip ([0035]: “the dummy dies 40 are defective active dies that have been recycled”). Yu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the dummy chip in that it would reduce warpage of the package ([0015]: “reduce warpage of the package”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to include the claimed dummy chip because it would reduce warpage. MPEP 2143 (I)(G).
Allowable Subject Matter
Claims 15-20 are allowed.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 15-20 is the inclusion of the limitation “wherein the interposer includes an inspection pattern disposed on an upper portion of the interposer, wherein the inspection pattern includes a test element group and/or a wafer alignment key, and wherein a second spacing distance between the inspection pattern and a lateral surface of the interposer is greater than a first spacing distance between a lateral surface of the base chip and an extension surface that extends from the lateral surface of the interposer, the lateral surface of the base chip being adjacent to the extension surface” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first spacing distance”, “second spacing distance”, and these distances related as claimed and as measured from the lateral surfaces claimed, in combination with all other limitations in claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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