Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/8/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 1-4 and 6-11, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 20210305145 A1) in view of Choi (US 20210175133 A1).
Regarding claim 1, Huang discloses a semiconductor package (Fig. 10), comprising:
a package substrate (200);
an interposer (140) disposed on the package substrate in a vertical direction (on in the Z direction, See annotated figure for direction designation) perpendicular to an upper surface of the package substrate;
a first semiconductor chip (110) disposed on the interposer (on in the Z direction) in the vertical direction; and
an inspection pattern including a test element group and/or a wafer alignment key,
wherein the interposer includes:
a first semiconductor substrate (141, See annotated figure); and
a first dielectric layer (a layer of 144; [0019]: one of the plural “passivation layers”) disposed on the first semiconductor substrate (on in the Z direction),
wherein a lateral surface of the interposer (lateral surface at PL, See annotated figure. Note: the region designated by the dashed reference lines as a portion of 140 that isn’t including PL) is defined by a lateral surface of the first dielectric layer that is coplanar (“coplanar” along the Z direction) with a lateral surface of the first semiconductor substrate in the vertical direction,
wherein the first dielectric layer includes a first scribe lane region (See annotated figure for dashed reference lines. Note: this region is interpreted here consistent with at least Fig. 2: region SR of Applicant’s disclosure.),
wherein the inspection pattern is disposed on the first scribe lane region,
wherein the first scribe lane region is below the first semiconductor chip (See annotated figure for “below” designation; “below” because it is at a lower height, without any particular required overlap in this direction) along the vertical direction, and
wherein the first scribe lane region and an entirety of the inspection pattern are spaced apart in a horizontal direction (apart in the X direction, See annotated figure for direction designation) from the lateral surface of the interposer.
Illustrated below is a marked and annotated figure of Fig. 10 of Huang.
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Huang discloses the semiconductor package and teaches the interposer, however fails to teach an inspection pattern. Thus, Huang fails to teach:
“an inspection pattern including a test element group and/or a wafer alignment key,
[…]
wherein the inspection pattern is disposed on the first scribe lane region,
[…]
wherein the first scribe lane region and an entirety of the inspection pattern are spaced apart in a horizontal direction from the lateral surface of the interposer.”
Choi discloses:
an inspection pattern (Fig. 33: 49A) including a test element group ([0037]: “a test element group”) and/or a wafer alignment key,
[…]
wherein the inspection pattern is disposed on the first scribe lane region (SL11),
[…]
wherein the first scribe lane region and an entirety of the inspection pattern are spaced apart in a horizontal direction from the lateral surface of the interposer (SW1).
Modifying the first scribe lane region of Huang by including the inspection pattern of Choi would arrive at the claimed interposer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each case the scribe lane region includes a semiconductor substrate (Huang: substrate 141, [0018]: “a semiconductor material”: Choi: substrate 21, [0039]: “a semiconductor substrate”). Choi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the inspection pattern in that it would enable early detection of manufacturing defects ([0037]: “may be electrically tested for determining whether elements of the chip regions CH are suitably formed on the wafer in a manufacturing process”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed inspection pattern because it would enable early detection of manufacturing defects. MPEP 2143 (I)(G).
Illustrated below is Fig. 33 of Choi.
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Regarding claim 2, Huang in view of Choi discloses the semiconductor package of claim 1 (Huang: Fig. 10), wherein the first scribe lane region has a tetragonal ring shape (See annotated Fig. 9, a top-down view of Fig. 10) having an inner edge (See annotated figure, a region edge, without any particular structural definition) and an outer edge (See annotated figure, a region edge, without any particular structural definition), and wherein the inner edge and the outer edge each overlap the first semiconductor chip (overlap in at least a diagonal direction different from the Z direction).
Illustrated below is a marked and annotated figure of Fig. 9 of Huang.
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Regarding claim 3, Huang in view of Choi discloses the semiconductor package of claim 1 (Huang: Fig. 10), wherein the first scribe lane region has a tetragonal ring shape (See annotated Fig. 9, a top-down view of Fig. 10) having an inner edge (See annotated figure, a region edge, without any particular structural definition) and an outer edge (See annotated figure, a region edge, without any particular structural definition), and wherein the inner edge overlaps the first semiconductor chip (overlap in at least a diagonal direction different from the Z direction), and the outer edge is exposed by the first semiconductor chip (“exposed” because the 1st chip doesn’t overlap this edge in the Z direction).
Regarding claim 4, Huang in view of Choi discloses the semiconductor package of claim 1 (Huang: Fig. 10), wherein the first dielectric layer further includes a dummy region (See annotated figure. Note: this region is interpreted here consistent with at least Fig. 2: region DR of Applicant’s disclosure.) that at least partially surrounds the first scribe lane region (fully surrounds in the top-down view of Fig. 9), and wherein at least a portion of the dummy region is positioned in a diagonal direction with respect to the first semiconductor chip (diagonal direction different from the Z direction).
Regarding claim 6, Huang in view of Choi discloses the semiconductor package of claim 4 (Choi: Fig. 33), further comprising a passivation layer (35A) that covers the first dielectric layer (31), wherein the inspection pattern includes an exposure pattern (45), and wherein the exposure pattern is exposed by the passivation layer (partially exposed).
Regarding claim 7, Huang in view of Choi discloses the semiconductor package of claim 6 (Choi: Fig. 1), wherein the passivation layer covers the first scribe lane region (partially covers) and exposes the dummy region (SLC1, corresponds to dummy region of Huang).
Regarding claim 8, Huang in view of Choi discloses the semiconductor package of claim 1 (Huang: Fig. 10), wherein the first semiconductor chip includes:
a second semiconductor substrate (112); and
a second dielectric layer (116; [0015]: “passivation layer”) disposed on the second semiconductor substrate (on in the Z direction),
wherein the second dielectric layer includes a second scribe lane region (See annotated figure),
wherein the first scribe lane region has a first width in a second direction (See annotated figure for direction designation) parallel to a top surface of the first semiconductor substrate,
wherein the second scribe lane region has a second width in the second direction (See annotated figure for direction designation), and
wherein the first width is greater than the second width (See additional remarks below. There are no specific structural boundaries for either the first or second scribe lane regions in the reference or the claim. Thus, these regions may be arbitrarily chosen within scope of Huang’s disclosure to include the claimed “greater than” configuration).
Further regarding the scribe lane region relative sizes (i.e., “wherein the first width is greater than the second width”), Huang illustrates the claimed scribe regions but is silent regarding their particular width measurement positions (i.e., dimensions). However, the claim as written reasonably encompasses a plurality of interpretations of these regions, without requiring any particular reconfiguration of the package. Thus, Huang appears to disclose regions that may be variably defined consistent with the claim. Therefore, the claimed relative dimensions of the regions would have been prima facie obvious to one of ordinary skill in the art before the effective filing date because they are not patentably distinct from the package disclosed by Huang. MPEP 2111; MPEP 2144.04 (IV)(A).
Regarding independent claim 9, Huang discloses a semiconductor package (Fig. 10), comprising:
a package substrate (200);
an interposer (140) stacked on the package substrate in a vertical direction (on in the Z direction, See annotated figure for direction designation) perpendicular to an upper surface of the package substrate;
a semiconductor chip (110) stacked on the interposer (on in the Z direction) in the vertical direction, and
a pair of sub-semiconductor packages (120/130) that are spaced apart in a horizontal direction (apart in the X direction, See annotated figure for direction designation) from each other across the semiconductor chip;
wherein the interposer includes:
a first semiconductor substrate (141, See annotated figure); and a
first dielectric layer (a layer of 144; [0019]: one of the plural “passivation layers”) disposed on the first semiconductor substrate (on in the Z direction),
wherein the first dielectric layer includes:
a wiring region (See annotated figure for dashed reference lines. Note: this region is interpreted here consistent with at least Fig. 2: region AR of Applicant’s disclosure.);
a scribe lane region (See annotated figure for dashed reference lines. Note: this region is interpreted here consistent with at least Fig. 2: region SR of Applicant’s disclosure.) that at least partially surrounds the wiring region (See annotated Fig. 9, a top-down view of Fig. 10); and
a dummy region (See annotated figure. Note: this region is interpreted here consistent with at least Fig. 2: region DR of Applicant’s disclosure.) that at least partially surrounds the scribe lane region (See annotated Fig. 9, a top-down view of Fig. 10), wherein at least a portion of the dummy region at least partially surrounds the semiconductor chip (Fig. 10 shows at least partial surrounding at a different Z height), and
wherein the scribe lane region overlaps each of the pair of sub-semiconductor packages in the vertical direction.
Huang teaches the scribe lane region and the vertical direction, but fails to teach the claimed configuration “wherein the scribe lane region overlaps each of the pair of sub-semiconductor packages in the vertical direction” because Huang illustrates functional components extending beyond the Z direction footprint of the sub-semiconductor packages. Thus, it is not reasonable to designate any of the Z direction footprint of the sub-semiconductor packages as the scribe lane.
Choi discloses wherein the scribe lane region (Fig. 38: encircled, See annotated figure) overlaps each of the pair of sub-semiconductor packages (See annotated figure) in the vertical direction (See annotated figure for direction designation). Choi differs from Huang because Choi teaches an alternative arrangement of parts within the interposer (i.e., the functional components). This alternative arrangement of parts illustrates: 1) functional components entirely within the Z direction footprint of the sub-semiconductor packages, when approaching the scribe lane region; and 2) additional empty space within the Z direction footprint of the sub-semiconductor packages. Thus, it is reasonable to designate at least some of the Z direction footprint of the sub-semiconductor packages as the scribe lane.
Accordingly, the claimed arrangement of the “scribe lane region” (i.e., “wherein the scribe lane region overlaps each of the pair of sub-semiconductor packages in the vertical direction”) appears to be an alternative position of the scribe lane region (alternative to Huang), based on alternative positions or shifting of functional components found elsewhere in the art (based on Choi). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success incorporating the claimed scribe lane region configuration because in each situation the functional components are performing the same function (Huang: Fig. 10: wiring region, See annotated figure; Choi: Fig. 38: pads and wirings, See annotated figure). Therefore, claimed arrangement of “the scribe lane region” is unpatentable because it is an arrangement/position/shifting of “the scribe lane region” designation found elsewhere within the prior art, performing the same function, and within the breadth of the claim. MPEP 2144.04 (VI)(C) Rearrangement of Parts; MPEP 2111 Broadest Reasonable Interpretation.
Illustrated below is a marked and annotated figure of Fig. 38 of Choi.
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Regarding claim 10, Huang in view of Choi discloses the semiconductor package of claim 9 (Huang: Fig. 10), wherein a lateral surface of the first semiconductor substrate (surface of 141 at PL) is coplanar (coplanar in the Z direction) with a lateral surface of the first dielectric layer (surface of 144 at PL), and wherein the lateral surface of the first dielectric layer is an outer edge of the dummy region (See annotated figure for edge designation).
Regarding claim 11, Huang in view of Choi discloses the semiconductor package of claim 9 (Huang: Fig. 10), further comprising an underfill pattern (150) disposed between the semiconductor chip and the interposer (between in the Z direction), wherein the underfill pattern covers the dummy region (indirectly covers in a diagonal direction).
Regarding claim 13, Huang in view of Choi discloses the semiconductor package of claim 9 (Huang: Fig. 10), wherein the semiconductor chip is a logic chip or a memory chip ([0014]: “a logic die”).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in view of Choi as applied to claim 9 above, and further in view of Yang (US 20220157777 A1).
Regarding claim 14, Huang in view of Choi discloses the semiconductor package of claim 9 (Huang: Fig. 10),
wherein the semiconductor chip is a dummy chip, and wherein the dummy chip includes:
a second semiconductor substrate (112; [0016]: “semiconductor materials”); and
a metal pad (114; [0016]: “metal pads”) in direct contact with the second semiconductor substrate (direct contact is illustrated).
Huang in view of Choi fails to teach “the semiconductor chip is a dummy chip”.
Yu discloses a semiconductor package (Fig. 1D) with a semiconductor chip (40), wherein the semiconductor chip is a dummy chip ([0042]: “dummy dies”), and wherein the dummy chip includes: a second semiconductor substrate ([0035]: “silicon”); and a metal pad (this “pad” is a required interface for [0042]: “the dummy dies 40 can be reflowed”) in direct contact with the second semiconductor substrate.
Modifying the semiconductor package of Huang in view of Choi, by including a semiconductor chip (structurally of Huang) that is a dummy chip (according to the teachings of Yu) would arrive at the claimed chip configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Yu teaches a dummy chip may be made from a repurposed chip ([0035]: “the dummy dies 40 are defective active dies that have been recycled”). Yu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the dummy chip in that it would reduce warpage of the package ([0015]: “reduce warpage of the package”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to include the claimed dummy chip because it would reduce warpage. MPEP 2143 (I)(G).
Allowable Subject Matter
Claims 15-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 15-20 is the inclusion of the limitation “wherein the interposer includes an inspection pattern disposed on an upper portion of the interposer, wherein the inspection pattern includes a test element group and/or a wafer alignment key, and wherein a second spacing distance between the inspection pattern and a lateral surface of the interposer is greater than a first spacing distance between a lateral surface of the base chip and an extension surface that extends from the lateral surface of the interposer, the lateral surface of the base chip being adjacent to the extension surface” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “first spacing distance”, “second spacing distance”, and these distances related as claimed and as measured from the lateral surfaces claimed, in combination with all other limitations in claim 15.
Response to Arguments
Applicant's arguments filed 6/23/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Huang fails to anticipate claim 1 as amended”. Remarks at pg. 8.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Choi is relied upon in the instant Office action to overcome the contended limitations.
Applicant argues:
Applicant argues with respect to amended claim 1 that “in Choi, lateral surfaces of the substrate 21 and the insulation layers 31, 33, and 35 are not coplanar with each other in the vertical direction as claimed. Furthermore, the test pad 45, which is a portion of the first pattern group 49A, as illustrated in FIG. 33 of Choi is vertically coplanar with, not spaced apart horizontally from, the right hand lateral surface of the insulation layer 33. That is, an entirety of the first pattern group 49A is not spaced apart from a lateral surface analogous to the claimed lateral surface of the interposer”. Remarks at pg. 8.
Examiner’s reply:
The examiner disagrees and points to MPEP 2111. The entirety of the test patter (Choi: Fig. 33: pattern 49) is spaced apart from a lateral surface of the interposer (SWL) and this lateral surface includes a first semiconductor substrate (21) and a first dielectric layer (23 or 31). These structures correspond to the substrate, and dielectric layer, and lateral surface of Huang. Accordingly, Huang in view of Choi is relied upon in the instant Office action based on these related features among the references.
Applicant argues:
Applicant argues with respect to amended claim 9 that “There is no portion of the interposer 140 of Huang that could reasonably correspond with the claimed scribe lane region overlapping the semiconductor dies 120 and 130 in the vertical direction as claimed”. Remarks at pg. 9.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Choi is relied upon in the instant Office action to overcome the contended limitations.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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