Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-3, 7-8 are rejected under 35 U.S.C. l12(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2-3, 7-8 recites “the verify read operation” where the limitations are very unclear and indefinite.
Because in claim 1 recite “performs a read operation or a verify read operation” where operation can be “read operation” or “verify read operation” i.e. only one operation. If we consider only “read operation”, then the limitation “the verify read operation” is totally unclear and indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Antonyan (US Pub # 2021/0319839).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Antonyan teaches a memory device comprising: a memory cell including a variable resistance element (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0108, M1…Mn memory cell, MTJ resistive element); a controller configured to generate a control signal based on whether the memory device performs a read operation or a verify read operation (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0108, unit 17 is controller, step S600 read operation); a reference cell including a reference resistance circuit configured to have different resistance values depending on the control signal (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0108, R1…Rn reference cell, R_REF is resistance circuit); and a sense amplifier configured to sense a difference between a read voltage value applied from the memory cell and a reference voltage value applied from the reference resistance circuit (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0108, unit AMP is sense amplifier, sensing voltage between sense node NS and reference node NR).
Even though Antonyan teaches resistance values (R_REF) for the reference cell but silent exclusively about “reference resistance circuit”. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Antonyan where resistor R_REF only added to reference cell which would be called reference resistance circuit in order to have improved reliability and performance of memory device (see paragraph 0108).
Regarding claim 2, Antonyan further teaches wherein the controller is configured to generate the control signal based on a target data value when the memory device performs the verify read operation (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, controller 17).
Regarding claim 3, Antonyan further teaches, wherein the reference resistance circuit, when the memory device performs the verify read operation and the target data value is a first value, is configured to have a first reference resistance value less than a specific reference resistance value, the specific reference resistance value being a resistance value of the reference resistance circuit when the memory device performs the read operation, and when the memory device performs the verify read operation the target data value is a second value, is configured to have a second reference resistance value greater than the specific reference resistance value (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0106).
Regarding claim 4, Antonyan further teaches, wherein the reference resistance circuit includes a plurality of resistance elements and a plurality of switching elements, and the reference resistance circuit is configured to change a resistance value thereof as the plurality of switching elements are turned on or off by the control signal (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0087).
Regarding claim 5, Antonyan further teaches, wherein the reference resistance circuit comprises: a first resistance element configured to be connected to the sense amplifier; a second resistance element configured to be connected in series with the first resistance element; a third resistance element connected in series with the second resistance element; a first switching element configured to be turned on or off by the control signal and to be connected in parallel to the second resistance element and the third resistance element; and a second switching element configured to be turned on or off by the control signal and connected in parallel with the third resistance element (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0085).
Regarding claim 6, Antonyan further teaches, wherein the controller is configured to generate the control signal for controlling the first switching element to be turned off and the second switching element to be turned on when the memory device performs the read operation (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074).
Regarding claim 7, Antonyan further teaches wherein the controller is configured to generate the control signal for controlling both the first switching element and the second switching element to be turned on or both the first switching element and the second switching element to be turned off when the memory device performs the verify read operation (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0080).
Regarding claim 8, Antonyan further teaches, wherein the controller is configured to, generate the control signal for controlling both the first switching element and the second switching element to be turned on when the memory device performs the verify read operation and a target data value is a first value, and generate the control signal for controlling both the first switching element and the second switching element to be turned off when the memory device performs the verify read operation and the target data value is a second value (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0087).
Regarding claim 9, Antonyan further teaches, wherein a resistance value of each of the first resistance element, the second resistance element, and the third resistance element is set based on a distribution of resistance values of the variable resistance element (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088).
Regarding claim 10, Antonyan further teaches, wherein the reference resistance circuit further includes a distribution circuit configured to generate a first signal input to the first switching element and a second signal input to the second switching element based on the control signal (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074).
Regarding independent claim 14, Antonyan teaches a memory device comprising: a memory cell including a variable resistance element (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0108, M1…Mn memory cell, MTJ resistive element); a reference cell including a reference resistance circuit having a reference resistance value corresponding to a resistance value of the variable resistance element (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0108, R1…Rn reference cell, R_REF is resistance circuit); a controller configured to generate a control signal based on whether the memory device performs a read operation or a verify read operation (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0108, unit 17 is controller, step S600 read operation); a first current supply circuit including a first current source and configured to apply a read current to the memory cell based on the control signal; a second current supply circuit including a second current source and configured to apply a reference current to the reference resistance circuit based on the control signal; and a sense amplifier configured to sense a difference between a read voltage value applied from the memory cell and a reference voltage value applied from the reference resistance circuit (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0108, unit AMP is sense amplifier, sensing voltage between sense node NS and reference node NR).
Even though Antonyan teaches resistance values (R_REF) for the reference cell but silent exclusively about “reference resistance value”. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Antonyan where resistor R_REF only added to reference cell which have resistance value in order to have improved reliability and performance of memory device (see paragraph 0108).
Regarding claim 15, Antonyan further teaches, wherein the second current supply circuit comprises: a third current source connected in parallel with the second current source and selectively increasing the reference current; a first switch adjusting a first connection between the second current source and the third current source based on the control signal; a fourth current source connected in parallel with the reference cell and selectively reducing the reference current; and a second switch adjusting a second connection between the reference cell and the fourth current source based on the control signal (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0108).
Regarding claim 16, Antonyan further teaches, wherein a current value flowing through each of the first current source, the second current source, the third current source, and the fourth current source is set based on a distribution of resistance values of the variable resistance element (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074).
Regarding claim 17, Antonyan further teaches, wherein the first current supply circuit comprises: a fifth current source connected in parallel with the first current source and selectively increasing the read current; a third switch adjusting a first connection between the first current source and the fifth current source based on the control signal; a sixth current source connected in parallel with the memory cell and selectively reducing the read current; and a fourth switch adjusting a second connection between the memory cell and the sixth current source based on the control signal (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099).
Regarding claim 18, Antonyan further teaches, wherein a current value flowing through each of the first current source, the second current source, the fifth current source, and the sixth current source is set based on a distribution of resistance values of the variable resistance element (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088).
Regarding claim 19, Antonyan further teaches wherein the first current supply circuit comprises: a fifth current source connected in parallel with the first current source and selectively increasing the read current; and a third switch adjusting a first connection between the first current source and the fifth current source based on the control signal, and the second current supply circuit comprises: a third current source connected in parallel with the second current source and selectively increasing the reference current; and a first switch adjusting a second connection between the second current source and the third current source based on the control signal (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0105).
Regarding claim 20, Antonyan further teaches wherein the first current supply circuit comprises: a sixth current source connected in parallel with the memory cell and selectively reducing the read current; and a fourth switch adjusting a connection between the memory cell and the sixth current source based on the control signal, and the second current supply circuit comprises: a fourth current source connected in parallel with the reference cell and selectively reducing the reference current; and a second switch adjusting the connection between the reference cell and the fourth current source based on the control signal (see Fig.1-3, 5-6, 10-16 and paragraph 0005-0008, 0026-0034, 0036-0048, 0054-0064, 0074, 0087-0088, 0099-0107).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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