DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/7/2023 and 12/14/2023 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract is consistent with the requirements set forth in the MPEP 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING CELL GATE CONDUCTIVE LAYER WITH TOP SURFACE AT DIFFERENT LEVELS
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. US PGPub. 2021/0118886. Regarding claim 10, Choi teaches a semiconductor device (fig. 11-13) [0021]-[0023], comprising: a substrate (100, fig. 13) [0029] including a first cell active pattern (AP1, fig. 13 and examiner’s fig. 1) [0031] and a dummy active pattern (IP1, fig. 13) [0036]; a cell gate dielectric layer (150, fig. 13) [0090] on the first cell active pattern (AP1) and the dummy active pattern (IP1); a cell gate conductive layer (140, fig. 13) [0090] on the cell gate dielectric layer (150); and a bit-line structure (BL, fig. 13) [0104] electrically connected (via 220 and 105a, fig. 12, [0113]) to the first cell active pattern (AP1), wherein the cell gate conductive layer (140) includes, a dummy overlap section (DOS, examiner’s fig. 1) overlapping the dummy active pattern (IP1), and a cell overlap section (COS, examiner’s fig. 1) overlapping the first cell active pattern (AP1), and wherein a maximum thickness (DT2’, examiner’s fig. 1) of the dummy overlap section (DOS) is greater than a maximum thickness (DTR1’, examiner’s fig. 1) of the cell overlap section (AP1) (Choi et al., fig. 13 and examiner’s fig. 1).
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Examiner’s Fig. 1
Regarding claim 11, Choi teaches the semiconductor device of claim 10, wherein the substrate (100) further includes a second cell active pattern (AP2, examiner’s fig. 1) adjacent to the dummy active pattern (IP1), and the dummy overlap section (DOS) overlaps the second cell active pattern (AP2) (Choi et al., fig. 13 and examiner’s fig. 1).
Allowable Subject Matter
Claims 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor device wherein “the dummy overlap section includes: a first part overlapping the dummy active pattern; and a second part overlapping the second cell active pattern, wherein a lowermost portion of the first part of the dummy overlap section is at a level higher than a level of a lowermost portion of the second part of the dummy overlap section” as recited in claim 12 in combination with the rest of the limitations of claims 10-11; and a semiconductor device wherein “a top surface of the cell overlap section is at a level lower than a level of a top surface of the dummy overlap section, and the semiconductor device further comprises a cell gate capping layer in contact with the top surface of the cell overlap section and the top surface of the dummy overlap section” as recited in claim 18 in combination with the rest of the limitations of claim 10.
Claims 13-17 are also objected to as allowable for further limiting and depending upon allowable claim 12. Claims 1-9 and 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior arts of record taken alone or in combination neither anticipates nor renders obvious a semiconductor device wherein “the first cell gate conductive layer includes, a dummy overlap section overlapping the dummy active pattern and the second cell active pattern, and a cell overlap section overlapping the first cell active pattern, and wherein a top surface of the dummy overlap section is at a level higher than a level of a top surface of the cell overlap section” as recited in claim 1; and a semiconductor device comprising “a second cell gate conductive layer on the first cell gate conductive layer” in combination with the limitation wherein “the first cell gate conductive layer includes, a first top surface in contact with the second cell gate conductive layer, and a second top surface in contact with the cell gate capping layer, and wherein the first top surface is at a level lower than a level of the second top surface” as recited in claim 19. Claims 2-9 and 20 are also allowed for further limiting and depending upon allowed claims 1 and 19. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jung et al. S PGPub. 2018/0226411 teaches a semiconductor device comprising first and second active patterns and a core region with dummy elements. Ryu et al. US PGPub. 2014/0131786 also teaches a semiconductor device comprising first and second active patterns and dummy patterns.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NDUKA E OJEH whose telephone number is (571)270-0291. The examiner can normally be reached M-F; 9am - 5pm..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NDUKA E OJEH/Primary Examiner, Art Unit 2892