DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
At this time Examiner is not requiring an election or restriction. Examiner reserves the right to require an election or restriction at a further time.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 7, 2023; July 16, 2024; May 5, 2025; and August 19, 2025 were considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 11-13, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasajima et al. (US 2013/0094120 A1) (“Sasajima”), in view of Kim et al. (US 2005/0112836 A1) (“Kim”).
Regarding claim 1, Sasajima teaches:
a substrate (12);
a capacitor (detailed below) including
a lower layer electrode (14),
a dielectric film (16), and
an upper layer electrode (18) sequentially laminated, from a side closest to the substrate, on a partial area of an upper surface serving as one surface of the substrate (this is shown in at least figures 3A-E); and
a coating (20) on or above the dielectric film (16),
the coating extending (20), when the upper surface is viewed in plan, throughout an edge of the lower layer electrode from an area inside the edge of the lower layer electrode to an area outside the edge (figures 3A-3E show the coating extending as required in a cross-section view. When said figures are viewed from the top they will form the claimed view), and
the coating (20) including an insulating metal oxide or a silicon oxide (¶ 0020).
Sasajima does not explicitly state:
a substrate including a compound semiconductor.
Sasajima teaches:
The MIM capacitor is made on a substrate is silicon ¶ 0020.
Kim teaches:
That one can make a MIM capacitor on either silicon or a compound semiconductor such as GaAs. ¶ 0031.
Therefore, it would have been obvious, as evidenced by Kim, one of ordinary skill in the art would know they could swap out the silicon substrate of Sasajima for a compound semiconductor as they are functionally equivalent in the art, and know obvious replacement for each other. MPEP 2144.06-07.
Regarding claim 2, Sasajima teaches:
wherein the coating (20) is thinner than the dielectric film (16) (¶ 0021, where 16 is 150 nm; ¶ 0022, where 20 is 82 nm).
Regarding claim 3, Sasajima teaches:
wherein an undercoat surface (20) of the coating includes (detailed below)
a flat area parallel to the upper surface of the substrate (there is a flat surface underneath 20), and
a step area on which a step is defined from side surfaces of the lower layer electrode (this is so shown in at least the abstract drawing), and
a thickness of a portion of the coating covering the step area is equal to a thickness of a portion of the coating covering the flat area (this is shown in at least the abstract drawing).
Regarding claim 4, Sasajima teaches:
wherein a metal oxide of the coating is at least one of an aluminium oxide, a hafnium oxide, a zirconium oxide, a titanium oxide, a tantalum oxide, a gallium oxide, a zinc oxide, and a strontium titanate (¶ 0022).
Regarding claim 11, Kim teaches:
wherein the compound semiconductor of the substrate is GaAs (¶ 0031)..
Regarding claim 12,
Claim 12 contains the same subject matter as claim 3 and is rejected for the same reason.
Regarding claim 13,
Claim 13 contains the same subject matter as claim 4 and is rejected for the same reason.
Regarding claim 18,
Claim 18 contains the same subject matter as claim 11 and is rejected for the same reason.
Regarding claim 19,
Claim 19 contains the same subject matter as claim 1 and is rejected for the same reason as claim 1 above.
Claim(s) 5, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasajima, in view of Kim, in view of Tsunetoshi et al. (WO 2010/082605) (“Tsunetoshi”) by means of machine translation.
Regarding claim 5, Sasajima teaches:
Where the coating (20) is above the upper layer electrode (18).
Sasajima does not teach:
wherein the coating is between the dielectric film and the upper layer electrode.
Tsunetoshi teaches at least in figure 4:
The capacitor’s dielectric can be made from a dual layer material (54-55). This dual layer material is one of ZrO2 and TiO2. TiO2 is the same material allowed by Applicant. Therefore, it can be treated at the coating material.
Tsunetoshi teaches that by adding TiO2 to the top of the MIM dielectric one can reduce the leakage current of the MIM capacitor at the same time increase the capacitance density of the MIM Capacitor. Pg. 5. As such it would have been obvious to one of ordinary skill in the art to modify Sasajima in order to gain the benefits described by Tsunetoshi.
Regarding claim 14,
Claim 14 contains the same subject matter as claim 5 and is rejected for the same reasons.
Regarding claim 20, Tsunetoshi teaches at least in figure 4:
wherein the coating (55) is formed by atomic layer deposition (Pg. 5).
Claim(s) 1, 6-9, and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2016/0035817 A1) (“Hsu”), in view of Kim et al. (US 2005/0112836 A1) (“Kim”).
Regarding claim 1, Hsu teaches:
a substrate (¶ 0030 not shown);
a capacitor (detailed below) including
a lower layer electrode (104),
a dielectric film (106), and
an upper layer electrode (108) sequentially laminated, from a side closest to the substrate, on a partial area of an upper surface serving as one surface of the substrate (this is shown in at least figure 1A); and
a coating (118) on or above the dielectric film (106),
the coating extending (118), when the upper surface is viewed in plan, throughout an edge of the lower layer electrode from an area inside the edge of the lower layer electrode to an area outside the edge (figures 1A show the coating extending as required in a cross-section view. When said figures are viewed from the top they will form the claimed view), and
the coating (118) including an insulating metal oxide or a silicon oxide (¶ 0043).
Sasajima does not explicitly state:
a substrate including a compound semiconductor.
Sasajima teaches:
The MIM capacitor is made on a substrate is silicon ¶ 0020.
Kim teaches:
That one can make a MIM capacitor on either silicon or a compound semiconductor such as GaAs. ¶ 0031.
Therefore, it would have been obvious, as evidenced by Kim, one of ordinary skill in the art would know they could swap out the silicon substrate of Sasajima for a compound semiconductor as they are functionally equivalent in the art, and know obvious replacement for each other. MPEP 2144.06-07.
Regarding claim 6, Hsu teaches:
wherein the coating (118) is on the upper layer electrode (108).
Regarding claim 7, Hsu teaches:
an insulator film (112) between the upper layer electrode (108) and the coating (118).
Regarding claim 8, Hsu teaches:
wherein when the upper surface is viewed in plan, an edge of the lower layer electrode and an edge of the upper layer electrode are at positions shifted from each other (while the shifting is not shown in the prior art this would have been obvious due to standard semiconductor process variations in each step of the semiconductor processing. For example this shift is called overlay in the photolithography process. Every tool ever invented for the semiconductor photolithography process has an inherent overlay. Overlay is the term for being able to put one layer on top of another. Thus, simply by the fact of using semiconductor processes to make the prior art device one would inherently, or obviously, manufacture a device with the claimed characteristics).
Regarding claim 9, Hsu teaches:
wherein when the upper surface is viewed in plan, a portion of the edge of the upper layer electrode is inward from the edge of the lower layer electrode, and a remaining portion of the edge of the upper layer electrode is outward from the edge of the lower layer electrode (this limitation is obvious for the same reasons given in claim 1 and 8 above.).
Regarding claim 15,
Claim 15 contains the same subject matter as claim 6 and is rejected for the same reasons.
Regarding claim 16,
Claim 16 contains the same subject matter as claim 7 and is rejected for the same reasons.
Regarding claim 17,
Claim 17 contains the same subject matter as claim 8 and is rejected for the same reasons.
Conclusion
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/VINCENT WALL/ Primary Examiner, Art Unit 2898