DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 8-11, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasajima et al. (US 2013/0094120 A1) (“Sasajima”), in view of Kim et al. (US 2005/0112836 A1) (“Kim”), with reference to Modafe, et al., "Embedded benzocyclobutene in silicon: An integrated fabrication process for electrical and thermal isolation in MEMS", Microelectronic Engineering, Volume 82, Issue 2, October 2005, Pages 154-167 (“Modafe”).
Regarding claim 1, Sasajima teaches:
a substrate (12);
a capacitor (detailed below) including
a lower layer electrode (14),
a dielectric film (16), and
an upper layer electrode (18) sequentially laminated, from a side closest to the substrate, on a partial area of an upper surface serving as one surface of the substrate (this is shown in at least figures 3A-E); and
a coating (20) on or above the dielectric film (16),
the coating extending (20), when the upper surface is viewed in plan, throughout an edge of the lower layer electrode from an area inside the edge of the lower layer electrode to an area outside the edge (figures 3A-3E show the coating extending as required in a cross-section view. When said figures are viewed from the top they will form the claimed view),
the coating (20) including an insulating metal oxide or silicon oxide (¶ 0020, where 20 can be Al2O3), and
an insulator film (22; ¶ 0023, where 22 is a BCB resin that formed over the entire device; BCB is an insulative resin as discussed in Modafe on pg. 155, col. 2 at ¶ 2) that continuously covers the lower layer electrode (14) and the upper layer electrode (18)
the coating (20) including an insulating metal oxide or a silicon oxide (¶ 0020),
wherein the coating (20) is thinner than the dielectric film (16) (¶ 0021, where 16 is 150 nm; ¶ 0022, where 20 is 82 nm).
Sasajima does not explicitly state:
a substrate including a compound semiconductor.
Sasajima teaches:
The MIM capacitor is made on a substrate is silicon ¶ 0020.
Kim teaches:
That one can make a MIM capacitor on either silicon or a compound semiconductor such as GaAs. ¶ 0031.
Therefore, it would have been obvious, as evidenced by Kim, one of ordinary skill in the art would know they could swap out the silicon substrate of Sasajima for a compound semiconductor as they are functionally equivalent in the art, and know obvious replacement for each other. MPEP 2144.06-07.
Regarding claim 3, Sasajima teaches:
wherein an undercoat surface (20) of the coating includes (detailed below)
a flat area parallel to the upper surface of the substrate (there is a flat surface underneath 20), and
a step area on which a step is defined from side surfaces of the lower layer electrode (this is so shown in at least the abstract drawing), and
a thickness of a portion of the coating covering the step area is equal to a thickness of a portion of the coating covering the flat area (this is shown in at least the abstract drawing).
Regarding claim 4, Sasajima teaches:
wherein a metal oxide of the coating is at least one of an aluminium oxide, a hafnium oxide, a zirconium oxide, a titanium oxide, a tantalum oxide, a gallium oxide, a zinc oxide, and a strontium titanate (¶ 0022).
Regarding claim 6, Sasajima teaches:
Where the coating (20) is above the upper layer electrode (18).
Regarding claim 8,
wherein when the upper surface is viewed in plan, an edge of the lower layer electrode and an edge of the upper layer electrode are at positions shifted from each other (while the shifting in a plan view is not shown, it would have been obvious that the edges of the lower electrode layer 14 and the upper electrode 18 would be shifted. This can be seen in at least figure 3 where the edges of 14 and 18 in the cross-sectional view are not coplanar. Rather, they are shifted from each other. Additionally, it would have been obvious due to standard semiconductor process variations in each step of the semiconductor processing. For example this shift is called overlay in the photolithography process. Every tool ever invented for the semiconductor photolithography process has an inherent overlay. Overlay is the term for being able to put one layer on top of another. Thus, simply by the fact of using semiconductor processes to make the prior art device one would inherently, or obviously, manufacture a device with the claimed characteristics).
Regarding claim 9,
wherein when the upper surface is viewed in plan, a portion of the edge of the upper layer electrode is inward from the edge of the lower layer electrode, and a remaining portion of the edge of the upper layer electrode is outward from the edge of the lower layer electrode (this limitation is obvious for the same reasons given in claim 8 above.).
Regarding claim 10,
Claim 10 is obvious for the same, or similar, reasons as claim 8 above, in that standard process variations, such as overlay, can create the claimed subject matter.
Regarding claim 11, Kim teaches:
wherein the compound semiconductor of the substrate is GaAs (¶ 0031)..
Regarding claim 19,
Claim 19 contains the same subject matter as claim 1 and is rejected for the same reason as claim 1 above.
Claim(s) 5, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasajima, in view of Kim, with reference to Modafe, in view of Tsunetoshi et al. (WO 2010/082605) (“Tsunetoshi”) by means of machine translation.
Regarding claim 5, Sasajima teaches:
Where the coating (20) is above the upper layer electrode (18).
Sasajima does not teach:
wherein the coating is between the dielectric film and the upper layer electrode.
Tsunetoshi teaches at least in figure 4:
The capacitor’s dielectric can be made from a dual layer material (54-55). This dual layer material is one of ZrO2 and TiO2. TiO2 is the same material allowed by Applicant. Therefore, it can be treated at the coating material.
Tsunetoshi teaches that by adding TiO2 to the top of the MIM dielectric one can reduce the leakage current of the MIM capacitor at the same time increase the capacitance density of the MIM Capacitor. Pg. 5. As such it would have been obvious to one of ordinary skill in the art to modify Sasajima in order to gain the benefits described by Tsunetoshi.
Regarding claim 20, Tsunetoshi teaches at least in figure 4:
wherein the coating (55) is formed by atomic layer deposition (Pg. 5).
Response to Arguments
Applicant’s amendments filed May 11, 2026 overcame the Hsu reference and its rejection. However, the amendments did not overcome the Sasajima reference.
Examiner used element 22 of Sasajima as the “an insulator film”. Sasajima teaches this is a BCB resin, and is a known alternative to SiO2 as shown in the Modafe reference. Further, coating 20 as taught by Sasajima is a metal oxide, Al2O3, as taught in ¶ 0020. Element 20 as shown in figure 2E covers the entire device.
For the above reasons, Applicant’s arguments are not persuasive.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VINCENT WALL/ Primary Examiner, Art Unit 2898
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