DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-8, 15-16 and 19-22 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by KWON (US 20230326925).
Regarding claim 1, KWON discloses a semiconductor structure, comprising:
a first field effect transistor (FET) of a first charge carrier type (lower transistor 410 which can be an NFET, see fig 4, para 82 and 75), comprising a first source/drain (S/D) region (fig 4, 414, para 82), a second S/D region (fig 4, 413, para 82), and a first set of one or more channels (the lower channel structure 212 which will be present in the device 40 of fig 4 since 40 has the same channel structure as 30 which has the same channel structure as 20, see fig 2, para 58, 71 and 82) that electrically connect the first S/D region to the second S/D region through a first gate structure (fig 4, 411, para 82);
a second FET of a second charge carrier type (upper transistor 420 which can be a PFET, see fig 4, para 82 and 75), disposed above the first FET in a Z direction (420 is above 410 in D3, which can be the z direction, see fig 4A) and comprising a third S/D (fig 4, 424, para 82) region disposed above the first S/D region (424 is above 414, see fig 4), a fourth S/D region (fig 4, 423, para 82), and a second set of one or more channels (the upper channel structure 222 which will be present in the device 40 of fig 4 since 40 has the same channel structure as 30 which has the same channel structure as 20, see fig 2, para 58, 71 and 82) that electrically connect the third S/D region to the fourth S/D region through a second gate structure (fig 4, 421, para 82); and
a vertical connector (the elements including MI, 417 and MI which connect 414 and 424, see fig 4A, para 83 and 85) extending in the Z direction from a top surface of the first S/D region to a bottom surface of the third S/D region (MI, 417 and MI extend in D3 and connect 414 and 424, see fig 4) and electrically coupling the first S/D region to the third S/D region.
Regarding claim 2, KWON discloses the semiconductor structure of claim 1, wherein the first gate structure comprises a first gate-all-around (GAA) structure comprising a first GAA region (the lower channel 212 is surrounded by the gate 211, see fig 2B, para 61) and wherein the second gate structure comprises a second GAA structure comprising a second GAA region (the upper channel 222 is surrounded by the gate 221, see fig 2B, para 61).
Regarding claim 5, KWON discloses the semiconductor structure of claim 1, wherein the vertical connector comprises a bottom portion comprising a first material (the bottom implanted portion MI, see fig 4, para 85), and a top portion comprising a second material (the upper implanted portion MI, see fig 4, para 85), disposed above and in contact with the bottom portion (the upper portion MI is above the lower portion MI, and is indirectly in contact with it via 417, see fig 4, para 85).
Regarding claim 6, KWON discloses the semiconductor structure of claim 5, wherein the bottom portion comprises a bottom contact material and wherein the top portion comprises a top contact material (top and bottom portions MI enable ohmic contact, see fig 4, para 85).
Regarding claim 7, KWON discloses the semiconductor structure of claim 1, wherein the vertical connector comprises a first material (417 can be Si, see fig 4, para 85).
Regarding claim 8, KWON discloses the semiconductor structure of claim 7, wherein the first material comprises a bottom contact material or a top contact material (417 can be Si, which contacts the top and bottom source/drain regions, see fig 4, para 49 and 85).
Regarding claim 15, KWON discloses a method of fabricating a semiconductor structure, the method comprising:
providing a first field effect transistor (FET) of a first charge carrier type (lower transistor 410 which can be an NFET, see fig 4, para 82 and 75), comprising providing a first source/drain (S/D) region (fig 4, 414, para 82), providing a second S/D region (fig 4, 413, para 82), and providing a first set of one or more channels (the lower channel structure 212 which will be present in the device 40 of fig 4 since 40 has the same channel structure as 30 which has the same channel structure as 20, see fig 2, para 58, 71 and 82) that electrically connect the first S/D region to the second S/D region through a first gate structure (fig 4, 411, para 82);
providing a second FET of a second charge carrier type (upper transistor 420 which can be a PFET, see fig 4, para 82 and 75), disposed above the first FET in a Z direction (420 is above 410 in D3, which can be the z direction, see fig 4A), comprising providing a third S/D region (fig 4, 424, para 82) disposed above the first S/D region, providing a fourth S/D region (fig 4, 423, para 82), and providing a second set of one or more channels (the upper channel structure 222 which will be present in the device 40 of fig 4 since 40 has the same channel structure as 30 which has the same channel structure as 20, see fig 2, para 58, 71 and 82) that electrically connect the third S/D region to the fourth S/D region through a second gate structure (fig 4, 421, para 82); and
providing a vertical connector (the elements including MI, 417 and MI which connect 414 and 424, see fig 4A, para 83 and 85) extending in the Z direction from a top surface of the first S/D region to a bottom surface of the third S/D region and electrically coupling the first S/D region to the third S/D region (MI, 417 and MI extend in D3 and connect 414 and 424, see fig 4) .
Regarding claim 18, KWON discloses the method of claim 15, wherein providing the first FET comprises providing a gate-all-around (GAA) FET comprising a first GAA region (the lower channel 212 is surrounded by the gate 211, see fig 2B, para 61) and wherein providing the second FET comprises providing a GAA FET comprising a second GAA region (the upper channel 222 is surrounded by the gate 221, see fig 2B, para 61).
Regarding claim 19, KWON discloses the method of claim 15, wherein providing the vertical connector comprises providing a bottom portion comprising a first material (the bottom implanted portion MI, see fig 4, para 85), and providing a top portion comprising a second material (the upper implanted portion MI, see fig 4, para 85), disposed above and in contact with the bottom portion (the upper portion MI is above the lower portion MI, and is indirectly in contact with it via 417, see fig 4, para 85).
Regarding claim 20, KWON discloses the method of claim 19, wherein providing the bottom portion comprises providing a bottom contact material and wherein providing the top portion comprises providing a top contact material (top and bottom portions MI enable ohmic contact, see fig 4, para 85).
Regarding claim 21, KWON discloses the method of claim 15, wherein providing the vertical connector comprises providing a first material (417 can be Si, see fig 4, para 85).
Regarding claim 22, KWON discloses the method of claim 21, wherein providing the first material comprises providing a bottom contact material or providing a top contact material (417 can be Si, which contacts the top and bottom source/drain regions, see fig 4, para 49 and 85).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-4, 9, 17-18 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON (US 20230326926) in view of HONG (US 20220344481).
Regarding claim 3, KWON discloses the semiconductor structure of claim 2, wherein:
the first FET comprises a first plurality of nanosheet channels (nanosheet channels 212, see fig 2B and 4, para 61 and 82) extending in an X direction (212 extends in D1, see fig 2 and 4), spaced apart from each other in the Z direction to from a first vertical stack (the different nanosheets are spaced apart in D3, see fig 2), electrically coupling the first S/D region to the second S/D region through the first GAA region (212 extends through the gate to connect s/d elements, see fig 2 and 4, para 61 and 82), and
the second FET comprises a second plurality of nanosheet channels (nanosheet channels 222, see fig 2B and 4, para 61 and 82) extending in the X direction (222 extends in D1, see fig 2 and 4), spaced apart from each other in the Z direction to from a second vertical stack (the different nanosheets are spaced apart in D3, see fig 2 and 4) disposed above the first vertical stack in the Z direction, electrically coupling the third S/D region to the fourth S/D region through the second GAA region (222 extends through the gate to connect s/d elements, see fig 2 and 4, para 61 and 82),
KWON fails to explicitly disclose a device wherein the first nanosheet channel being separated from the first GAA region by a first dielectric material; and
the second nanosheet channel being separated from the second GAA region by a second dielectric material.
HONG teaches a device wherein the first nanosheet channel being separated from the first GAA region by a first dielectric material (gate insulator 24L_1, see fig 5, para 28); and
the second nanosheet channel being separated from the second GAA region by a second dielectric material (gate dielectric 24U_1, see fig 5, para 28).
KWON and HONG are analogous art because they both are directed towards 3-D arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the gate dielectrics of HONG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the gate dielectrics of HONG in order to avoid increasing device area (see HONG para 16).
Regarding claim 4, KWON discloses the semiconductor structure of claim 1.
KWON fails to explicitly disclose a device, wherein each of the first S/D region and the second S/D region comprises an epitaxial structure that extends in an X direction to an adjacent gate structure and wherein each of the third S/D region and the fourth S/D region comprises a small, discontinuous epitaxial (SDE) structure that extends in the X direction a distance less than a distance to the adjacent gate structure.
HONG teaches a device, wherein each of the first S/D region and the second S/D region comprises an epitaxial structure that extends in an X direction to an adjacent gate structure (the lower source/drain structures 26L extend from one gate structure 25 to another, see fig 7, para 37) and wherein each of the third S/D region and the fourth S/D region comprises a small, discontinuous epitaxial (SDE) structure that extends in the X direction a distance less than a distance to the adjacent gate structure (the upper source/drain structures 26U do not extend all the way from one upper gate structure 25U to another, see fig 7, para 37).
KWON and HONG are analogous art because they both are directed towards 3-D arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the source/drain configuration of HONG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the source/drain configuration of HONG in order to avoid increasing device area (see HONG para 16).
Regarding claim 9, KWON discloses the semiconductor structure of claim 8.
KWON fails to explicitly disclose a device, wherein the first material comprises at least one of tungsten, cobalt, or molybdenum.
HONG teaches a device, wherein the first material comprises at least one of tungsten (the conductor 34 can be W, see fig 2, para 38), cobalt, or molybdenum.
KWON and HONG are analogous art because they both are directed towards 3-D arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the conductor material of HONG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the conductor material of HONG in order to avoid increasing device area (see HONG para 16).
Regarding claim 17, KWON discloses the semiconductor structure of claim 2, wherein:
providing the first FET comprises providing a first plurality of nanosheet channels (nanosheet channels 212, see fig 2B and 4, para 61 and 82) extending in an X direction (212 extends in D1, see fig 2 and 4), spaced apart from each other in the Z direction to from a first vertical stack (the different nanosheets are spaced apart in D3, see fig 2), electrically coupling the first S/D region to the second S/D region through the first GAA region (212 extends through the gate to connect s/d elements, see fig 2 and 4, para 61 and 82), and
providing the second FET comprises providing a plurality of nanosheet channels (nanosheet channels 222, see fig 2B and 4, para 61 and 82) extending in the X direction (222 extends in D1, see fig 2 and 4), spaced apart from each other in the Z direction to from a second vertical stack (the different nanosheets are spaced apart in D3, see fig 2 and 4) disposed above the first vertical stack in the Z direction, electrically coupling the third S/D region to the fourth S/D region through the second GAA region (222 extends through the gate to connect s/d elements, see fig 2 and 4, para 61 and 82).
KWON fails to explicitly disclose a method, wherein the first channels being separated from the first GAA region by a first dielectric material; and
the second channels being separated from the second GAA region by a second dielectric material.
HONG teaches a method, wherein the first channel being separated from the first GAA region by a first dielectric material (gate insulator 24L_1, see fig 5, para 28); and
the second channels being separated from the second GAA region by a second dielectric material (gate dielectric 24U_1, see fig 5, para 28).
KWON and HONG are analogous art because they both are directed towards 3-D arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KWON with the gate dielectrics of HONG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KWON with the gate dielectrics of HONG in order to avoid increasing device area (see HONG para 16).
Regarding claim 18, KWON discloses the method of claim 15.
KWON fails to explicitly disclose a method, wherein providing each of the first S/D region and the second S/D region comprises providing an epitaxial structure that extends in an X direction to an adjacent gate structure and wherein providing each of the third S/D region and the fourth S/D region comprises providing a small, discontinuous epitaxial (SDE) structure that extends in the X direction a distance less than a distance to the adjacent gate structure.
HONG teaches a method, wherein providing each of the first S/D region and the second S/D region comprises providing an epitaxial structure that extends in an X direction to an adjacent gate structure (the lower source/drain structures 26L extend from one gate structure 25 to another, see fig 7, para 37) and wherein providing each of the third S/D region and the fourth S/D region comprises providing a small, discontinuous epitaxial (SDE) structure that extends in the X direction a distance less than a distance to the adjacent gate structure (the upper source/drain structures 26U do not extend all the way from one upper gate structure 25U to another, see fig 7, para 37).
KWON and HONG are analogous art because they both are directed towards 3-D arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KWON with the source/drain configuration of HONG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KWON with the source/drain configuration of HONG in order to avoid increasing device area (see HONG para 16).
Regarding claim 23, KWON discloses the method of claim 22.
KWON fails to explicitly disclose a method, wherein providing the first material comprises providing at least one of tungsten, cobalt, or molybdenum.
HONG teaches a method, wherein providing the first material comprises providing at least one of tungsten (the conductor 34 can be W, see fig 2, para 38), cobalt, or molybdenum.
KWON and HONG are analogous art because they both are directed towards 3-D arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KWON with the conductor material of HONG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of KWON with the conductor material of HONG in order to avoid increasing device area (see HONG para 16).
Claim(s) 10-14 and 24-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON (US 20230326926) in view of YU (US 20230062026).
Regarding claim 10, KWON discloses the semiconductor structure of claim 1.
KWON fails to explicitly disclose a device, further comprising:
a frontside metal (FM) layer disposed above the first FET in the Z direction and comprising a plurality of FM conductors extending in an X direction and spaced apart from each other in a Y direction; and
a backside metal (BM) layer disposed below the second FET in the Z direction and comprising a plurality of BM conductors extending in the X direction and spaced apart from each other in the Y direction.
YU teaches a device, further comprising:
a frontside metal (FM) layer disposed above the first FET in the Z direction (the three upper conductors 232 above the lower device 171, see fig 20, para 71) and comprising a plurality of FM conductors extending in an X direction and spaced apart from each other in a Y direction (232 extend in the gate length direction of 106 and are spaced apart perpendicular to that direction, see fig 20, para 71); and
a backside metal (BM) layer disposed below the second FET in the Z direction (the three lower conductors 236 below the upper device 186, see fig 20, para 71) and comprising a plurality of BM conductors extending in the X direction and spaced apart from each other in the Y direction (236 extend in the gate length direction of 106 and are spaced apart perpendicular to that direction, see fig 20, para 71).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Regarding claim 11, KWON discloses the semiconductor structure of claim 10.
KWON fails to explicitly disclose a device, wherein the plurality of FM conductors extending in the X direction consists of four or fewer FM conductors extending in the X direction.
YU teaches a device, wherein the plurality of FM conductors extending in the X direction consists of four or fewer FM conductors extending in the X direction (there are three conductors 232, see fig 20).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Regarding claim 12, KWON discloses the semiconductor structure of claim 10.
KWON fails to explicitly disclose a device, wherein the plurality of BM conductors extending in the X direction consists of four or fewer BM conductors extending in the X direction.
YU teaches a device, wherein the plurality of BM conductors extending in the X direction consists of four or fewer BM conductors extending in the X direction (there are three conductors 236, see fig 20).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Regarding claim 13, KWON discloses the semiconductor structure of claim 10.
KWON fails to explicitly disclose a device, wherein the plurality of FM conductors extending in the X direction consists of three or fewer FM conductors extending in the X direction.
YU teaches a device, wherein the plurality of FM conductors extending in the X direction consists of three or fewer FM conductors extending in the X direction (there are three conductors 232, see fig 20).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Regarding claim 14, KWON discloses the semiconductor structure of claim 10.
KWON fails to explicitly disclose a device, wherein the plurality of BM conductors extending in the X direction consists of three or fewer BM conductors extending in the X direction.
YU teaches a device, wherein the plurality of BM conductors extending in the X direction consists of three or fewer BM conductors extending in the X direction (there are three conductors 236, see fig 20).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Regarding claim 24, KWON discloses the method of claim 15.
KWON fails to explicitly disclose a method, further comprising:
providing a frontside metal (FM) layer disposed above the first FET in the Z direction and comprising a plurality of FM conductors extending in an X direction and spaced apart from each other in a Y direction; and
providing a backside metal (BM) layer disposed below the second FET in the Z direction and comprising a plurality of BM conductors extending in the X direction and spaced apart from each other in the Y direction.
YU teaches a method, further comprising:
providing a frontside metal (FM) layer disposed above the first FET in the Z direction (the three upper conductors 232 above the lower device 171, see fig 20, para 71) and comprising a plurality of FM conductors extending in an X direction and spaced apart from each other in a Y direction (232 extend in the gate length direction of 106 and are spaced apart perpendicular to that direction, see fig 20, para 71); and
providing a backside metal (BM) layer disposed below the second FET in the Z direction (the three lower conductors 236 below the upper device 186, see fig 20, para 71) and comprising a plurality of BM conductors extending in the X direction and spaced apart from each other in the Y direction (236 extend in the gate length direction of 106 and are spaced apart perpendicular to that direction, see fig 20, para 71).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to method the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Regarding claim 25, KWON discloses the method of claim 24.
KWON fails to explicitly disclose a method, wherein providing the plurality of FM conductors extending in the X direction consists of providing four or fewer FM conductors extending in the X direction.
YU teaches a method, wherein providing the plurality of FM conductors extending in the X direction consists of providing four or fewer FM conductors extending in the X direction (there are three conductors 232, see fig 20).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to method the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Regarding claim 26, KWON discloses the method of claim 24.
KWON fails to explicitly disclose a method, wherein providing the plurality of BM conductors extending in the X direction consists of providing four or fewer BM conductors extending in the X direction.
YU teaches a method wherein providing the plurality of BM conductors extending in the X direction consists of providing four or fewer BM conductors extending in the X direction (there are three conductors 236, see fig 20).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to method the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Regarding claim 27, KWON discloses the method of claim 24.
KWON fails to explicitly disclose a method, wherein providing the plurality of FM conductors extending in the X direction consists of providing three or fewer FM conductors extending in the X direction.
YU teaches a method, wherein providing the plurality of FM conductors extending in the X direction consists of providing three or fewer FM conductors extending in the X direction (there are three conductors 232, see fig 20).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to method the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Regarding claim 28, KWON discloses the method of claim 24.
KWON fails to explicitly disclose a method, wherein providing the plurality of BM conductors extending in the X direction consists of providing three or fewer BM conductors extending in the X direction.
YU teaches a method, wherein providing the plurality of BM conductors extending in the X direction consists of providing three or fewer BM conductors extending in the X direction (there are three conductors 236, see fig 20).
KWON and YU are analogous art because they both are directed towards arrays of FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of KWON with the upper and lower contacts of YU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to method the device of KWON with the upper and lower contacts of YU in order to reduce the issue of mixed Vt boundary for NFET and PFET (see YU para 72).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811