Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
Claim 17 is objected to because of the following informalities:
It appears that Applicant mistakenly included the following limitation “a silicon bridge structure bonded on the first pin-arrays of the two adjacent chips” twice in claim 17.For purpose of examination, the limitation will be considered only once.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Mahajan et al. (US 2015/0171015 A1) in view of Shen et al. (US 6,383,846 B1) and Pietambaram et al. (US 2020/0258847 A1).
Regarding independent claim 1: Mahajan teaches (e.g., Fig. 3 and Figs. 5-6) a method of manufacturing a chiplet-fine-interconnection-package structure, comprising:
mounting at least two chips ([0039]: step 501 chips 608 and 610) on a first side surface of a substrate ([0039]: top side of substrate 612) and
wherein the first surface of each chip (top surface of chip 608 and chip 610) includes a first pin-array ([0042]: 606) having a first spacing (Fig. 6. [0042]) and a second pin-array ([0042]: 604) having a second spacing (Fig. 6. [0042]);
preparing a package layer ([0035] and : 312) on a second side surface of the substrate (back side surface), and
bonding a silicon bridge structure ([0033], [0043]-[0044]: step 503; bridge 614) for electrically connecting the two adjacent chips (608 and 610) on the first pin-arrays (606) of the two adjacent chips,
preparing a build-up layer ([0047]: ”\encapsulation may be accomplished utilizing build-up layers”).
Mahajan does not expressly teach
preparing a temporary bonding layer covering a first surface of each one of the at least two chips,
preparing a plastic package layer on a second side surface of the substrate,
wherein the substrate is prepared with microvias to allow plastic package materials of the plastic package layer to flow from the microvias into an area between the first side surface of the substrate and the temporary bonding layer to prepare the plastic package layer which covers the substrate and the chips;
releasing the temporary bonding layer, and
preparing a build-up layer on the plastic package layer and
preparing a solder bump on the build-up layer such that the solder bump is electrically connected with the second pin-array through the build-up layer.
Shen teaches (e.g., Figs. 1-2 and 5-7) a method comprising:
preparing a temporary bonding layer (Col. 4, Lines 37-45: 11) covering a first surface of each one of the at least two chips (Col. 4, Lines 54-58: upper surface of chip 23),
preparing a plastic package layer (Col. 4, Lines 15-28: and 37-45: flowable encapsulant) on a second side surface of a substrate (37-45: upper side of substrate 20),
wherein the substrate is prepared with microvias (Col. 3, Lines 61-67 and Col. 4, Lines 48-58: 24) to allow plastic package materials of the plastic package layer to flow from the microvias into an area between the first side surface of the substrate (20) and the temporary bonding layer (11) to prepare the plastic package layer which covers the substrate (20) and the chip (23),
releasing the temporary bonding layer (Fig. 7, the temporary bonding layer 11 is removed).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Mahajan, the method of preparing a temporary bonding layer covering a first surface of each one of the at least one chip,
preparing a plastic package layer on a second side surface of the substrate, wherein the substrate is prepared with microvias to allow plastic package materials of the plastic package layer to flow from the microvias into an area between the first side surface of the substrate and the temporary bonding layer to prepare the plastic package layer which covers the substrate and the chip and releasing the temporary bonding layer, as taught by Shen, for the benefits of controlling the encapsulation process and suppressing voids in the packaging layer further protecting the device from environment humidity.
Pietambaram teaches (e.g., Figs. 1A-1B and 4A-4E) a method comprising
preparing a build-up layer ([0073] and [0083]: layer build-up from upper stacked layers 420/422) on a package layer ([0083]: lower layer 420) and preparing a solder bump ([0086]: 428) on the build-up layer such that the solder bump is electrically connected with a second pin-array ([0083]: array elements 419 represent pin array, based on size compared to pillars 424) through the build-up layer (420/422).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Mahajan as modified by Shen, the method of preparing a build-up layer on the plastic package layer and preparing a solder bump on the build-up layer such that the solder bump is electrically connected with the second pin-array through the build-up layer, as taught by Pietambaram, for the benefits of increasing the integrated circuit density by stacking and interconnecting more devices on the first devices, and thus increasing the integrated circuit functionalities.
Regarding claim 2: Mahajan, Shen and Pietambaram teach the claim limitation of the method as claimed in claim 1, on which this claim depends, further comprising:
Mahajan does not expressly teach
preparing an underfill in an area below each silicon bridge structure prior to preparing the build-up layer.
Pietambaram teaches a method comprising:
preparing an underfill ([0085]: 411) in an area below a silicon bridge structure ([0084]: 430) prior to preparing the build-up layer ([0073] and [0083]: layer build-up from upper stacked layers 420/422).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Mahajan as modified by Shen, the method comprising
preparing an underfill in an area below each silicon bridge structure prior to preparing the build-up layer, as taught by Pietambaram, for the benefits of enhancing product reliability and lifespan by protecting delicate components from mechanical and thermal stresses, by creating a strong mechanical bond between the chip and the substrate.
Claims 13, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mahajan et al. (US 2015/0171015 A1) in view of Pietambaram et al. (US 2020/0258847 A1).
Regarding independent claim 13: Mahajan teaches (e.g., Figs. 5-6) a chiplet-fine-interconnection-package structure manufactured by the methods as claimed in claim 7, comprising:
a substrate ([0039]: top side of substrate 612);
at least two chips ([0039]: step 501 chips 608 and 610) attached to a first side surface of the substrate (upper side of the substrate),
wherein each chip includes a first pin-array ([0042]: 606) having a first spacing and a second pin-array ([0042]: 604) having a second spacing;
a package layer ([0035]: 312);
a silicon bridge structure ([0033], [0043]-[0044]: 614) bonded on the first pin-arrays of the two adjacent chips;
a build-up layer ([0047]) disposed on the package layer.
Mahajan does not expressly teach
a plastic package layer;
a build-up layer disposed on the plastic package layer; and a solder bump arranged on the build-up layer,
wherein the solder bump is electrically connected to the second pin-array through the build-up layer and the plastic package layer.
Pietambaram teaches (e.g., Figs. 1A-1B and 4A-4E) a chiplet-fine-interconnection-package structure
a build-up layer ([0073] and [0083]: layer build-up from upper stacked layers 420/422) on a plastic package layer ([0083]: lower layer 420 is a mold layer, thus, it is a plastic material due to its flowable nature) and
a solder bump ([0086]: 428) on the build-up layer;
wherein the solder bump is electrically connected to the second pin-array ([0083]: array elements 419 represent pin array, based on size compared to pillars 424) through the build-up layer and the plastic package layer ([0073] and [0083]: layer build-up from upper stacked layers 420/422).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Mahajan as modified by Shen, the device comprising a plastic package layer, a build-up layer disposed on the plastic package layer; and a solder bump arranged on the build-up layer, wherein the solder bump is electrically connected to the second pin-array through the build-up layer and the plastic package layer, as taught by Pietambaram, for the benefits of increasing the integrated circuit density by stacking and interconnecting more devices on the first devices, and thus increasing the integrated circuit functionalities.
Regarding claim 17: Mahajan teaches (e.g., Figs. 5-6) a chiplet-fine-interconnection-package structure manufactured by the methods as claimed in claim 1, comprising:
a substrate ([0039]: top side of substrate 612);
at least two chips ([0039]: step 501 chips 608 and 610) attached to a first side surface of the substrate (upper side of the substrate),
wherein each chip includes a first pin-array ([0042]: 606) having a first spacing and a second pin-array ([0042]: 604) having a second spacing;
a silicon bridge structure ([0033], [0043]-[0044]: 614) bonded on the first pin-arrays (606) of the two adjacent chips;
a package layer ([0035]: 312);
a build-up layer ([0047]) disposed on the package layer;
Mahajan does not expressly teach
a plastic package layer;
a solder bump arranged on the build-up layer,
wherein the solder bump is electrically connected to the second pin-array through the build-up layer.
Pietambaram teaches (e.g., Figs. 1A-1B and 4A-4E) a package structure comprising:
a plastic package layer ([0083]: lower layer 420 is a mold layer, thus, it is a plastic material due to its flowable nature);
a build-up layer ([0073] and [0083]: layer build-up from upper stacked layers 420/422) on a plastic package layer ([0083]: lower layer 420 is a mold layer, thus, it is a plastic material due to its flowable nature) and
a solder bump ([0086]: 428) on the build-up layer;
wherein the solder bump (428) is electrically connected to a second pin-array ([0083]: array elements 419 represent pin array, based on size compared to pillars 424) through the build-up layer and the plastic package layer ([0073] and [0083]: layer build-up from upper stacked layers 420/422).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Mahajan as modified by Shen, the device comprising a plastic package layer, a build-up layer disposed on the plastic package layer; and a solder bump arranged on the build-up layer, wherein the solder bump is electrically connected to the second pin-array through the build-up layer and the plastic package layer, as taught by Pietambaram, for the benefits of increasing the integrated circuit density by stacking and interconnecting more devices on the first devices, and thus increasing the integrated circuit functionalities.
Regarding claim 20: Mahajan and Pietambaram teach the claim limitation of the package structure as claimed in claim 17, on which this depends.
Mahajan does not expressly teach that the package structure further comprises
an underfill in an area below the silicon bridge structure,
wherein the underfill is prepared using the same material as the plastic package layer or the first insulating material of the build-up layer, or the underfill is prepared using a different material from the plastic package layer and the first insulating material of the build-up layer.
Pietambaram teaches (e.g., Figs. 1A-1B and 4A-4E) a package structure comprising a build-up layer ([0073] and [0083]: layer build-up from upper stacked layers 420/422) and a silicon bridge structure ([0084]: 430);
Pietambaram further teaches
an underfill ([0085]: 411) in an area below the silicon bridge structure ([0084]: 430);
wherein the underfill (411) is prepared using a different material from a plastic package layer and the first insulating material of the build-up layer (Fig. 4D; mold layer 420 and build-up layer 422/420).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the packaging device of Mahajan, the underfill in an area below the silicon bridge structure, wherein the underfill is prepared using a different material from the plastic package layer and the first insulating material of the build-up layer, as taught by Pietambaram, for the benefits of enhancing product reliability and lifespan by protecting delicate components from mechanical and thermal stresses, by creating a strong mechanical bond between the chip and the substrate.
Allowable Subject Matter
Claims 3-6, 14-16 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method of manufacturing a chiplet-fine-interconnection-package structure, comprising:
“removing the plastic package layer which covers the second side surface of the substrate”.
Regarding claim 4: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method of manufacturing a chiplet-fine-interconnection-package structure, comprising:
“wherein the silicon bridge structure is a thinned silicon bridge with a temporary support structure, and the method further comprises:
releasing the temporary support structure of the silicon bridge structure after the silicon bridge structure is bonded to the first pin-arrays of the two adjacent chips”.
Claim 5 depends from claim 4, and therefore, is allowable for the same reason as claim 4.
Regarding claim 5. The method as claimed in claim 4, wherein the thinned silicon bridge is manufactured by:
fastening a silicon wafer having a first thickness to the temporary support structure through a temporary adhesive material;
performing a thinning process on the silicon wafer having the first thickness fastened on the temporary support structure; and preparing a fourth pin-array which is provided to bond the first pin-array of the chip and fine lines which is provided to electrically conduct with the fourth pin-array on the thinned silicon wafer such that the thinned silicon bridge with the temporary support structure is formed.
Regarding claim 6: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method of manufacturing a chiplet-fine-interconnection-package structure, comprising:
“the outermost layer of the build-up layer further includes a third pin-array arranged on a surface of the first insulating material, the third pin-array is electrically connected to the second pin-array through the first interconnect, and the solder bump is prepared on the third pin-array”.
Regarding claim 14: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a chiplet-fine-interconnection-package structure comprising:
“each build-up layer includes a first insulating material and a first interconnect formed in the first insulating material, and the outermost layer of the build-up layer further includes a third pin-array arranged on the surface of the first insulating material, the third pin-array is electrically connected to the second pin-array through the first interconnect, and the solder bump is arranged on the third pin-array.
Claims 15-16 depend from claim 14, and therefore, are allowable for the same reason as claim 14.
Regarding claim 18: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a chiplet-fine-interconnection-package structure comprising:
“wherein the plastic package layer covers both the substrate and the chip without covering a first surface of the chip, and the silicon bridge structure is covered by the innermost layer of the build-up layer”.
Regarding claim 19: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a chiplet-fine-interconnection-package structure comprising:
“wherein the substrate is prepared using a thermal conductivity material such as copper, and a second side surface of the substrate is not covered by the plastic package layer, or both the first side surface and the second side surface of the substrate are covered by the plastic package layer”.
Claims 7-12 are allowable.
Regarding claim 7: the most relevant prior art references Mahajan teaches (e.g., Figs. 5-6) a method of manufacturing a chiplet-fine-interconnection-package structure, comprising:
mounting at least two chips ([0039]: step 501 chips 608 and 610) on a first side surface of a substrate ([0039]: top side of substrate 612),
wherein each chip includes a first pin-array ([0042]: 606) having a first spacing and a second pin-array ([0042]: 604) having a second spacing;
bonding a silicon bridge structure ([0043]: step 503; bridge 614) for electrically connecting the two adjacent chips (608 and 610) on the first pin-arrays (606) of the two adjacent chips.
Shen fairly teaches (e.g., Figs. 1-2 and 5-7) a method comprising:
preparing a temporary bonding layer (Col. 4, Lines 37-45: 11) covering a first surface of each one of the at least two chips (Col. 4, Lines 54-58: upper surface of chip 23),
preparing a plastic package layer (Col. 4, Lines 15-28: and 37-45: flowable encapsulant) on a second side surface of a substrate (37-45: upper side of substrate 20),
wherein the substrate is prepared with microvias (Col. 3, Lines 61-67 and Col. 4, Lines 48-58: 24) to allow plastic package materials of the plastic package layer to flow from the microvias into an area between the first side surface of the substrate (20) and the temporary bonding layer (11) to prepare the plastic package layer which covers the substrate (20) and the chip (23),
releasing the temporary bonding layer (Fig. 7, the temporary bonding layer 11 is removed).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Mahajan, the method of preparing a temporary bonding layer covering a first surface of each one of the at least one chip,
preparing a plastic package layer on a second side surface of the substrate, wherein the substrate is prepared with microvias to allow plastic package materials of the plastic package layer to flow from the microvias into an area between the first side surface of the substrate and the temporary bonding layer to prepare the plastic package layer which covers the substrate and the chip and releasing the temporary bonding layer, as taught by Shen, for the benefits of controlling the encapsulation process and suppressing voids in the packaging layer further protecting the device from environment humidity.
Pietambaram fairly teaches (e.g., Figs. 1A-1B and 4A-4E) a method
preparing on the plastic package layer a solder bump electrically connected with the second pin-array through the plastic package layer, or preparing a build-up layer on the plastic package layer and preparing the solder bump electrically connected with the second pin-array through the plastic package layer and the build-up layer on the build-up layer, as shown above.
However, none of the prior art references either singly or in proper combination discloses or fairly suggests, along with the other claimed features, a method of manufacturing a chiplet-fine-interconnection-package structure, comprising:
“preparing a temporary bonding layer on the silicon bridge structure”.
Claims 8-12 depend from claim 7, and therefore, are allowable for the same reason as claim 7.
Conclusion
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/HERVE-LOUIS Y ASSOUMAN/Examiner, Art Unit 2812