DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 24 is rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Lee US 2017/0271353.
Regarding claim 24, Lee teaches a memory device (e.g., the device in Figs. 1-2 and Figs. 5-6, Fig. 8 (the manufacturing process of the device in Figs. 5-6), the description thereof; also see the device in Figs. 1-2 and Figs. 3-4 for additional details) comprising:
a memory cell array (e.g., memory cell array including CH (S_CH, P_CH, D_CH), Figs. 1-2, [25]) including a plurality of cell plugs (e.g., CHs, Figs. 1-2, [25], [26]);
a first slit (e.g., first slit; see the annotated Fig. 2 below) isolating the memory cell array into a plurality of memory regions (e.g., memory regions; see the annotated Fig. 2 below) including gate lines (e.g., WLs including CPn, Fig. 6A, [28]; Fig. 1), the first slit extending in a first direction (e.g., direction I; see the annotated Fig. 2 below);
second slits (e.g., second slits; see the annotated Fig. 2 below; [78]) penetrating the plurality of memory regions (e.g., Fig. 6A), the second slits spaced apart in a second direction (e.g., direction II; see the annotated Fig. 2 below) non-parallel to the first direction; and
third slits (e.g., third slits; see the annotated Fig. 2 below) spaced apart from each other in the second direction and spaced apart from the second slits in the first direction (e.g., see the annotated Fig. 2 below); and
wherein the gate lines are isolated from each other by the first slit (e.g., Fig. 2; Fig. 6A);
wherein each gate line located in the same layer among the gate lines included in each of the plurality of memory regions extends through a first connection region (e.g., first connection region; see the annotated Fig. 2 below; also see Fig. 6A (a cross-sectional view taken along line X-X’ of Fig. 2) and Fig. 6B (a cross-sectional view taken along line Z-Z’ of Fig. 5B)) between the second slits; and
wherein each of the second slits faces a corresponding one of the third slits in the first direction (e.g., each second slit (discussed above) faces, in the first direction (e.g., direction I; see the annotated Fig. 2 below), a portion of a corresponding one of the third slits (discussed above), which overlaps the second slit when viewed along the first direction; see the annotated Fig. 2 below).
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Annotated Fig. 2 of Lee
Response to Arguments
Applicant's arguments filed on June 14, 2026 have been fully considered but are moot in view of the new ground(s) of rejection as stated above.
Allowable Subject Matter
Claims 1-7, 10-12 and 19-23 are allowed at this time, pending updated search before the Examiner's next response, because the prior art of record neither anticipates nor render obvious the limitation of the base claim 1 that recites “third slits spaced apart from each other in a second direction and spaced apart from the second slits in the first direction; wherein each gate line located in the same layer among the gate lines included in each of the plurality of memory regions extends through a first connection region between the second slits; and wherein the first connection region does not overlap with the third slits in the first direction” in combination with other elements of the base claim 1.
Conclusion
The art made of record and not applied to the rejection is considered pertinent to applicant's disclosure. It is cited primarily to show inventions relevant to the examination of the instant invention. For example, Lee et al. US 2012/0146127 and Hong US 2012/0168858 relates to a memory device including gate lines included in each of the plurality of memory regions are isolated from each other by a slit.
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a) . Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a) .
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
If applicant should desire to file an amendment, entry of a proposed amendment after final rejection cannot be made as a matter of right unless it merely cancels claims or complies with a formal requirement made earlier. Amendments touching the merits of the application which otherwise might not be proper may be admitted upon a showing a good and sufficient reasons why they are necessary and why they were not presented earlier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 August 16, 2026
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