DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-12) in the reply filed on February 19, 2025 is acknowledged. Claims 13-18 drawn to non-elected invention have been canceled. New claims 19-22 depending from claim 1 have been added.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application KR 10-2023-0068232 filed in Korean Intellectual Property Office (KIPO) on May 26, 2023 and receipt of a certified copy thereof.
Information Disclosure Statement
The information disclosure statement (IDS) filed on November 7, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Objections
Claim 5 is objected to because of the following informality:
In claim 5, line 2, “each of gate lines” should read --each gate line--. Support can be found at least in line 10 of the base claim 1.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12, 19 and 22 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Lee US 20170271353.
Regarding claim 1, Lee teaches a memory device (e.g., the device in Figs. 1-2 and Figs. 5-6, Fig. 8 (the manufacturing process of the device in Figs. 5-6), the description thereof; also see the device in Figs. 1-2 and Figs. 3-4 for additional details) comprising:
a memory cell array (e.g., memory cell array including CH (S_CH, P_CH, D_CH), Figs. 1-2, [25]) including a plurality of cell plugs (e.g., CHs, Figs. 1-2, [25], [26]);
a first slit (e.g., first slit; see the annotated Fig. 2 below) isolating the memory cell array into a plurality of memory regions (e.g., memory regions; see the annotated Fig. 2 below), the first slit extending in a first direction (e.g., direction I; see the annotated Fig. 2 below); and
second slits (e.g., second slits; see the annotated Fig. 2 below; [78]) penetrating the plurality of memory regions (e.g., Fig. 6A), the second slits being arranged to be spaced apart from each other in a second direction (e.g., direction II; see the annotated Fig. 2 below) intersecting the first direction,
wherein gate lines (e.g., WLs including CPn, Fig. 6A, [28]; Fig. 1) included in each of the plurality of memory regions are isolated from each other by the first slit, and
wherein each gate line located in the same layer among the gate lines included in each of the plurality of memory regions extends through a first connection region (e.g., first connection region; see the annotated Fig. 2 below; also see Fig. 6A (a cross-sectional view taken along line X-X’ of Fig. 2) and Fig. 6B (a cross-sectional view taken along line Z-Z’ of Fig. 5B)) between the second slits for each corresponding memory region.
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Annotated Fig. 2 of Lee
Regarding claim 2, Lee teaches the memory device of claim 1, wherein each of the second slits is formed in substantially a quadrangular pillar shape or substantially a circular pillar shape (e.g., see the annotated Fig. 2 above).
Regarding claim 3, Lee teaches the memory device of claim 1, wherein a plane of each of the second slits includes a minor axis in the first direction (e.g., direction I; see the annotated Fig. 2 above) and a major axis in the second direction (e.g., direction II; see the annotated Fig. 2 above).
Regarding claim 4, Lee teaches the memory device of claim 1, further including a second connection region (e.g., second connection region; see the annotated Fig. 2 above) between the first slit and the second slits.
Regarding claim 5, Lee teaches the memory device of claim 4, wherein each of gate lines located in the same layer among the gate lines included in each of the plurality of memory regions extends through the first connection region and the second connection region (e.g., first connection region, second connection region; see the annotated Fig. 2 above; also see Fig. 6A (a cross-sectional view taken along line X-X’ of Fig. 2) and Fig. 6B (a cross-sectional view taken along line Z-Z’ of Fig. 5B)).
Regarding claim 6, Lee teaches the memory device of claim 5, wherein the gate lines included in each of the plurality of memory regions include: a source select line (e.g., SEL in CP_S, [30], [28], Fig. 1); word lines (e.g., WLs including CPn, Fig. 6A, [28]; Fig. 1) located on the source select line; and a drain select line (e.g., SEL in CP_D, [30], [28], Fig. 1) located on the word lines.
Regarding claim 7, Lee teaches the memory device of claim 6, further comprising an isolation pattern (e.g., isolation pattern (including the insulating layers SD2); see the annotated Fig. 2 above; Fig. 6A) isolating the drain select line along the first direction.
Regarding claim 8, Lee teaches the memory device of claim 1, further comprising third slits (e.g., third slits; see the annotated Fig. 2 above) spaced apart from the second slits in the first direction, the third slits penetrating the plurality of memory regions (e.g., Fig. 6A).
Regarding claim 9, Lee teaches the memory device of claim 8, wherein the third slits are spaced apart from each other in the second direction (e.g., direction II; see the annotated Fig. 2 above).
Regarding claim 10, Lee teaches the memory device of claim 8, wherein each of the third slits is formed in substantially a quadrangular pillar shape or substantially a circular pillar shape (e.g., see the annotated Fig. 2 above).
Regarding claim 11, Lee teaches the memory device of claim 8, wherein a plane of each of the third slits includes a minor axis in the first direction (e.g., direction I; see the annotated Fig. 2 above) and a major axis in the second direction (e.g., direction II; see the annotated Fig. 2 above).
Regarding claim 12, Lee teaches the memory device of claim 1, wherein each of the first and second slits is formed as a single layer or a multi-layer (e.g., SD1.SD2, Fig. 6A)
Regarding claim 19, Lee teaches the memory device of claim 1, wherein the second slits comprise an insulating layer (e.g., SD1, SD2, [62]).
Regarding claim 22, Lee teaches the memory device of claim 8, wherein a first distance between the second slits and the third slits in the first direction is substantially equal to a second distance between adjacent first slits in the second direction (e.g., the term “substantially equal to” does not necessarily mean --equal to--, thus, an arbitrary distance between the second slits and the third slits and an arbitrary distance between adjacent first slits are considered to be equal to each other).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20 and 21 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Lee US 20170271353 in view of Watarai et al. US 2022/0302155.
Regarding claim 20, Lee teaches the memory device of claim 1 as discussed above.
Lee does not explicitly teach wherein the second slits comprise a silicon layer.
Watarai teaches the second slits comprise a silicon layer (e.g., [73]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee to include wherein the second slits comprise a silicon layer as suggested by Watarai for the purpose of reducing the stress due to differences in material and thickness of layers adjacent to the slits for example (e.g., Watarai, [73], [68]). In this case,
Regarding claim 21, Lee teaches the memory device of claim 1 as discussed above.
Lee does not explicitly teach wherein at least one of the second slits comprises: a slit conductive layer; and a slit insulating layer surrounding the slit conductive layer.
Watarai teaches wherein at least one of the second slits comprises: a slit conductive layer; and a slit insulating layer surrounding the slit conductive layer (e.g., [73]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee to include wherein at least one of the second slits comprises: a slit conductive layer; and a slit insulating layer surrounding the slit conductive layer as suggested by Watarai for the purpose of reducing the stress due to differences in material and thickness of layers adjacent to the slits for example (e.g., Watarai, [73], [68]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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/BO B JANG/Primary Examiner, Art Unit 2818 March 6, 2026