DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/11/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5-11 & 22-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations “where a plurality of photoelectric conversion units and a plurality of transfer gates each configured to transfer signal charge generated in corresponding one of the plurality of photoelectric conversion units included in a plurality of pixels are arranged;” and “a plurality of amplifying transistors each including a gate to which the signal charge is input, and each configured to output a signal based on a voltage of the gate a second pixel region including a part of a pixel included in the plurality of pixels”. It is unclear what the limitations intend to describe as they are replete with punctuation and/or grammatical errors. Correction is required.
Claim 1 further recites “a first pixel region” in line 6. It is unclear if it refers to “a second pixel region” in line 20 or a different feature.
Claim 22 recites “a second pixel region” in line 29. It is unclear if it refers to “a first pixel region” in line 26 of claim 1 or a different feature
Claims 5-11 and 22-23 are rejected for being dependent on claim 1.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
As best understood, claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,843,886 (Shimotsusa et al) in view of Choi et al. (US Pub. 2011/0096215). Although the claims at issue are not identical, they are not patentably distinct from each other.
Regarding claim 1, Shimotsusa teaches in claims 1 and 11 a device comprising:
a first semiconductor substrate; and
a second semiconductor substrate overlapping the first semiconductor substrate, wherein the first semiconductor substrate includes a first pixel region where a plurality of photoelectric conversion units and each configured to transfer signal charge generated in corresponding one of the plurality of photoelectric conversion units included in a plurality of pixels are arranged;
wherein the second semiconductor substrate includes a gate to which the signal charge is input, and each configured to output a signal based on a voltage of the gate a second pixel region including a part of a pixel included in the plurality of pixels;
wherein a first pixel region includes the plurality of photoelectric conversion units and the plurality of transfer gates,
wherein a second pixel region includes the plurality of amplifying transistors, and
wherein in plan view, the first pixel region overlaps the second pixel region.
Shimotsusa is silent on wherein the first pixel region includes a plurality of transfer gates and wherein the second semiconductor includes a plurality of amplifying transistors to transfer and output signals.
However, Choi discloses wherein a first pixel region includes a plurality of transfer gates and a second substrate includes a plurality of amplifying transistors ([0010-0011, 0029-0030 & 0068]). This has the advantage of providing a high-speed electrical switch and minimal power consumption. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Shimotsusa with the transfer and amplifying transistors, as taught by Choi, so as to obtain an efficient semiconductor device.
Claims 511 and 22-23 are rejected for being dependent on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) the invention was known or used by others in this country, or patented or described in a printed publication in this or a foreign country, before the invention thereof by the applicant for a patent.
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claims 1, 5-11 & 23 are rejected under pre-AIA 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by Choi et al. (US Pub. 2011/0096215).
Regarding claim 1, Choi teaches a device comprising:
a first semiconductor substrate (100 or 200a, Fig. 3); and
a second semiconductor substrate (200a or 100) overlapping the first semiconductor substrate (Fig. 3), wherein the first semiconductor substrate(100 or 200a) includes a first pixel region where a plurality of photoelectric conversion units and a plurality of transfer gates each configured to transfer signal charge generated in corresponding one of the plurality of photoelectric conversion units included in a plurality of pixels are arranged (Fig. 2-3 and Para [0010-0011, 0017-0018, 0029-0030, 0033-0034, 0037 & 0066]);
wherein the second semiconductor substrate includes a plurality of amplifying transistors each including a gate to which the signal charge is input, and each configured to output a signal based on a voltage of the gate a second pixel region including a part of a pixel included in the plurality of pixels (Fig. 2-3 & Para [0068]);
wherein a first pixel region includes the plurality of photoelectric conversion units and the plurality of transfer gates (Fig. 2-3 and Para [0010-0011, 0017-0018, 0029-0030, 0033-0034, 0037 & 0066]),
wherein a second pixel region includes the plurality of amplifying transistors (Fig. 2-3 & Para [0068]), and
wherein in plan view, the first pixel region overlaps the second pixel region (note that a pixel region in 150 or substrate 100 overlaps a pixel region in 250 or 200a, see Fig. 3).
Regarding claim 23, Choi teaches a device according to claim 1, wherein a first circuit region (e.g. logic region) arranged around the second pixel region, wherein in plan view, at least a part of the first circuit region does not overlap the first pixel region (Fig. 3).
Regarding claim 5, Choi teaches a device according to claim 23, wherein a first circuit 10B arranged in the first circuit region includes a signal processing circuit for processing a signal output from the plurality of units (Fig. 3).
Regarding claim 6, Choi teaches a device according to claim 5, wherein the first circuit includes at least one of a vertical shift register, a column circuit unit, a signal holding unit, a horizontal shift register, and a difference amplifying unit (Fig. 2-3).
Regarding claim 7, Choi teaches a device according to claim 5, wherein the first circuit includes an analog-to-digital converter (Para [0061]).
Regarding claim 8, Choi teaches a device according to a device according to claim 23 wherein the first substrate includes a second circuit region arranged adjacent to the first unit region, and wherein in plan view, a first circuit arranged in the first circuit region overlaps the second circuit region (note some of the transistors in 150 and metallization circuits in 250 overlap one another, Fig. 2-3).
Regarding claim 9, Choi teaches a device according to claim 8, wherein a second circuit arranged in the second circuit region includes a part of a shift register (some of the transistors or metallization in 150 & 259 can be part of shift register circuitry).
Regarding claim 10, Choi teaches a device according to claim 8, wherein a connection portion between the first circuit and a second circuit arranged in the second circuit region is provided in a region (region including 224) overlapping the first circuit region in plan view (Fig. 3).
Regarding claim 11, Choi teaches a device according to claim 23, wherein a connection portion between the first substrate and the second substrate is provided in a region (region that includes 224) overlapping the first circuit region in plan view (see Fig. 3).
Allowable Subject Matter
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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