DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2, Fig. 17, item 11, claims 1-20, in the reply filed on March 11, 2026 is acknowledged. Action on the merits is as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KUO et al. (KUO) (US 2022/0223491 A1 now US 11,908,767 B2) in view of Tateiwa et al. (US 8,994,193 B2).
In regards to claim 1, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) discloses a semiconductor package (items 100, 300, 600, 700), comprising: a lower redistribution wiring layer (item 302) including first redistribution wirings (item 302c); a semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) on the lower redistribution wiring layer (item 302) and electrically connected to the first redistribution wirings (item 302c); a sealing member (item 320) on the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) on the lower redistribution wiring layer (item 302); a plurality of through vias (item 318) penetrating the sealing member (item 320) and electrically connected to the first redistribution wirings (item 302c); an upper redistribution wiring layer (item 322) on the sealing member (item 320) and having second redistribution wirings (item 322c) electrically connected to the plurality of through vias (item 318), wherein the second redistribution wirings (item 322c) includes buried wirings (item 322c) that are buried in a plurality of recesses formed in an insulating layer (item 322p) and electrically connected to the plurality of through vias (item 318); and upper redistribution wirings (item 322c) provided in at least one upper insulating layer (item 322p) on the sealing member (item 320), and electrically connected to the buried wirings (item 322c), but does not specifically disclose wherein the second redistribution wirings includes buried wirings that are buried in a plurality of recesses formed in an upper surface of the sealing member and electrically connected to the plurality of through vias.
Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein the second redistribution wirings (items 10 plus 64) includes buried wirings (item 10) that are buried in a plurality of recesses (portions where item 10 reside) formed in an upper surface of the sealing member (item 20) and electrically connected to the plurality of through vias (item 31C).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Tateiwa for the purpose of an electrical connection and protection/insulation.
In regards to claim 11, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) discloses a semiconductor package (items 100, 300, 600, 700), comprising: a lower redistribution wiring layer (item 302) including first redistribution wirings (item 302c); a semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) on the lower redistribution wiring layer (item 302), wherein the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) includes chip pads (items 106, 308) formed on a first surface of the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314), and wherein the first surface of the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) faces the lower redistribution wiring layer (item 302); a sealing member (item 320) on the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) on the lower redistribution wiring layer (item 302); a plurality of through vias (item 318) penetrating the sealing member (items 118, 320) and electrically connected to the first redistribution wirings (item 302C); and an upper redistribution wiring layer (items 120, 322) disposed on the sealing member (item 118, 320), wherein the second redistribution wirings (item 322c) includes buried wirings (item 322c) that are buried in a plurality of recesses formed in an insulating layer (item 322p) and electrically connected to the plurality of through vias (item 318); and upper redistribution wirings (item 322c) provided in at least one upper insulating layer (shown but not labeled in Fig. 1, item 322p) on the sealing member (item 320), and electrically connected to the buried wirings (item 322c), at least one upper insulating layer (shown but not labeled in Fig. 1, item 322p) on the upper surface of the sealing member (item 118, 320); and upper redistribution wirings (shown but not labeled in Fig. 1, item 322C) provided in the at least one upper insulating layer (shown but not labeled in Fig. 1, item 322p) but does not specifically disclose wherein the upper redistribution wiring layer includes: buried wirings formed in recesses of an upper surface of the sealing member and electrically connected to the plurality of through vias.
Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein the upper redistribution wiring layer (items 10 plus 64) includes: includes buried wirings (item 10) that are buried in recesses (portions where item 10 reside) of an upper surface of the sealing member (item 20) and electrically connected to the plurality of through vias (item 31C).
Therefore, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) as modified by Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein the upper redistribution wiring layer (items 10 plus 64) includes: includes buried wirings (item 10) that are buried in recesses (portions where item 10 reside) of an upper surface of the sealing member (items 118, 320, KUO, item 20, Tateiwa) and electrically connected to the plurality of through vias (items 116, 318, KUO, item 31C, Tateiwa); at least one upper insulating layer (shown but not labeled in Fig. 1, item 322p, KUO) on the upper surface of the sealing member (items 118, 320, KUO, item 20, Tateiwa); and upper redistribution wirings (item 322C, KUO) provided in the at least one upper insulating layer (item 322p, KUO) and electrically connected to the buried wirings (item 10, Tateiwa).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Tateiwa for the purpose of an electrical connection and protection/insulation.
In regards to claims 2 and 12, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) as modified by Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein at least one of the buried wirings (item 10, Tateiwa) partially contact the plurality of through vias (items 318, KUO, item 31C, Tateiwa).
In regards to claims 3 and 13, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) as modified by Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein at least one of the buried wirings (item 10, Tateiwa) contact an upper sidewall of the plurality of through vias (items 318, KUO, item 31C, Tateiwa). Examiner notes the Applicant has not given a special definition to the term “contact”, therefore certain features can be in “direct” or “indirect” contact with one another.
It would have been obvious to modify the invention to include buried wirings that contact an upper sidewall of the plurality of through vias, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention buried wirings that contact an upper sidewall of the plurality of through vias, since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
In regards to claims 4 and 14, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) as modified by Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein an upper surface of the buried wirings (item 10, Tateiwa) and the upper surface of the sealing member (item 320, KUO, item 20, Tateiwa) are coplanar.
In regards to claims 5 and 15, KUO as modified by Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein a thickness of a buried wiring (item 10) of the plurality of buried wirings is within a range of 3 μm to 20 μm (col. 4, lines 2-14, 15 to 70 μm), including endpoints.
However, the applicant has not established the critical nature of a thickness of a buried wiring of the plurality of buried wirings being within a range of 3 μm to 20 μm. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests inside and outside the claimed range to show criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197(CCPA 1960). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have various ranges.
In regards to claims 6 and 16, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) discloses wherein the sealing member (items 118, 320) includes a first sealing portion covering an upper surface of the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) and a second sealing portion covering an upper surface of the lower redistribution wiring layer (items 102, 302) around the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314).
Therefore it would have been obvious to one of ordinary skill in the art before the effective to combine teachings of the several embodiments of KUO for the purpose of various device package configurations.
In regards to claims 7 and 17, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) as modified by Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein the buried wirings (item 10, Tateiwa) are provided on an upper surface of the first sealing portion (item 118, 320, KUO, item 20, Tateiwa) and an upper surface of the second sealing portion (item 118, 320, KUO, item 20, Tateiwa).
In regards to claims 8 and 18, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) discloses wherein the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) is mounted on the lower redistribution wiring layer (items 102, 302) via conductive bumps (items 106, 308, paragraphs 28, 60).
In regards to claim 9, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) discloses wherein the sealing member (item 118, 320) exposes an upper surface of the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314).
In regards to claims 10 and 19, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) discloses further comprising a second package (items 100b, 300b) disposed on the upper redistribution wiring layer (items 122, 322), wherein the second package includes a package substrate (items 124, 326) and at least one second semiconductor chip (items 126, 328) on the package substrate (items 124, 326).
In regards to claim 20, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) discloses a semiconductor package (items 100, 300, 600, 700), comprising: a lower redistribution wiring layer (item 302) including first redistribution wirings (item 302c); a semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) on the lower redistribution wiring layer (item 302), wherein the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) includes chip pads (items 106, 308) formed on a first surface (bottom surface) of the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314), and wherein the first surface (bottom surface) of the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) faces the lower redistribution wiring layer (item 302); a sealing member (item 320) on the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) on the lower redistribution wiring layer (item 302) and exposing a second surface (top surface) of the semiconductor chip (items 108 or 108 pls 110 plus 112, items 310 or 310 plus 312 plus 314) opposite to the first surface (bottom surface); a plurality of through vias (item 318) penetrating the sealing member (items 118, 320) and electrically connected to the first redistribution wirings (item 302C); and an upper redistribution wiring layer (items 120, 322) disposed on the sealing member (item 118, 320) and having second redistribution wirings (shown but not labeled in Fig. 1, item 322C) electrically connected to the through vias (items 116, 318); wherein the upper redistribution wirings (item 322c) includes buried wirings (item 322c) that are buried in a plurality of recesses formed in an insulating layer (item 322p) and electrically connected to the plurality of through vias (item 318); and upper redistribution wirings (item 322c) provided in at least one upper insulating layer (shown but not labeled in Fig. 1, item 322p) on the sealing member (item 320), and electrically connected to the buried wirings (item 322c), at least one upper insulating layer (shown but not labeled in Fig. 1, item 322p) on the upper surface of the sealing member (item 118, 320); and upper redistribution wirings (shown but not labeled in Fig. 1, item 322C) provided in the at least one upper insulating layer (shown but not labeled in Fig. 1, item 322p) but does not specifically disclose wherein the upper redistribution wiring layer includes: buried wirings formed in recesses of an upper surface of the sealing member and electrically connected to the plurality of through vias.
Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein the upper redistribution wiring layer (items 10 plus 64) includes: includes buried wirings (item 10) that are buried in recesses (portions where item 10 reside) of an upper surface of the sealing member (item 20) and electrically connected to the plurality of through vias (item 31C).
Therefore, KUO (Figs. 1, 3, 5A, 5B, 6, 7 and associated text and equivalent items) as modified by Tateiwa (Figs. 5A, 6 and associated text and items) discloses wherein the upper redistribution wiring layer (items 10 plus 64) includes: includes buried wirings (item 10) that are buried in recesses (portions where item 10 reside) of an upper surface of the sealing member (items 118, 320, KUO, item 20, Tateiwa) and electrically connected to the plurality of through vias (items 116, 318, KUO, item 31C, Tateiwa); at least one upper insulating layer (shown but not labeled in Fig. 1, item 322p, KUO) on the upper surface of the sealing member (items 118, 320, KUO, item 20, Tateiwa); and upper redistribution wirings (item 322C, KUO) provided in the at least one upper insulating layer (item 322p, KUO) and electrically connected to the buried wirings (item 10, Tateiwa).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Tateiwa for the purpose of an electrical connection and protection/insulation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. All prior art listed in the 892 could have been used as a primary reference. Lee et al. (US 2022/0102309 A1, Figs. 40, 41) discloses a heat sink and thermal interface material applied to the package as well. Examiner suggests that the Applicant perfect foreign priority.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 May 10, 2026
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