DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1, Embodiment I, Figs. 1-2B, claims 1-11, in the reply filed on February 11, 2026 is acknowledged. However, Examiner notes that claim 5 does not belong with the elected species. Claim 5 belongs with non-elected Species 4, which has first and second silicon grains. Therefore, Claims 5 and 12-20 have been withdrawn. Action on the merits is as follows:
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang (US 2017/0200724 A1 now US 9,704,872 B1).
In regards to claim 1, Huang (Fig. 2G and associated text) discloses a semiconductor memory device (item 200, Fig. 2G) comprising: a device isolation part (item 240) on a substrate (item 210), the device isolation part (item 240) defining a first active portion (item 222) and a second active portion (item 224), a center portion of the first active portion (item 222) adjacent in a first direction to an edge portion of the second active portion (item 224 [not shown if Figures, but implicitly disclosed since Huang discloses DRAM with buried word line architecture); a first impurity region (item 222) in the center portion of the first active portion; a second impurity region (item 224) in the edge portion of the second active portion; a first bit line (item 250) in direct contact with the first impurity region (item 222) and crossing the substrate (item 210) in a second direction, the second direction intersecting the first direction; and a storage node contact (item 272) in contact with the second impurity region (item 224), wherein an upper end of the first impurity region (item 222) is higher than an upper end of the second impurity region (item 224), and wherein an upper sidewall (upper inner sidewall) of the storage node contact (item 272) is not vertically aligned with a lower sidewall (lower inner sidewall) of the storage node contact (item 272), the upper sidewall (upper inner sidewall) and the lower sidewall (lower inner sidewall) both on a common side of the storage node contact (item 272).
In regards to claim 2, Huang (Fig. 2G and associated text) discloses further comprising: a second bit line (item 250 on the right) extending in the second direction and spaced apart from the first bit line (item 250 on the left) in the first direction, the storage node contact (item 272) interposed between the second bit line (item 250 on the right) and the first bit line (item 250 on the left); and a bit line spacer (item 252) interposed between the second bit line (item 250 on the right) and the storage node contact (item 272), wherein a lower portion of the storage node contact (item 272) is below the bit line spacer (item 252).
In regards to claim 3, Huang (Fig. 2G and associated text) discloses further comprising an interlayer insulating layer (item 262) interposed between the second bit line (item 250 on the right) and the device isolation part (item 240), wherein an upper portion of the interlayer insulating layer (items 258 plus 264) has a first width (width of item 258 plus 264), and wherein a lower portion of the interlayer insulating layer (items 262) has a second width smaller (width of item 262) than the first width (width of item 258 plus 264).
In regards to claim 10, Huang (Fig. 2G and associated text) discloses further comprising a bit line spacer (items 264 plus 258 plus 254) interposed between the first bit line (item 250 on the left) and the storage node contact (item 272), wherein the bit line spacer (items 264 plus 258 plus 254) includes first, second, and third sub-spacers (items 264, 258 and 254) sequentially on sidewalls of the first bit line (item 250 on the left), wherein lower portions of the first and second sub-spacers (item 268 and 258) extend across a lower surface of the third sub-spacer (item 254).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 6-9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2017/0200724 A1 now US 9,704,872 B1) in view of Kim et al. (Kim) (US 2022/0173107 A1 now US 11,631,677 B2).
In regards to claim 4, Huang does not specifically disclose wherein the common side of the storage node contact has an inflection point between the upper sidewall and the lower sidewall.
Kim (Fig. 1B and associated text) discloses wherein the common side of the storage node contact (item BC) has an inflection point (item PT1) between the upper sidewall (upper inner sidewall of item BC) and the lower sidewall (lower inner sidewall of item BC).
It would have been obvious to modify the invention to include a common side of the storage node contact having an inflection point between the upper sidewall and the lower sidewall, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 6, Kim (Figs. 1A, 1B and associated text) discloses wherein the device isolation part (item 302) is interposed between the first impurity region (item 312a) and the second impurity region (item 312b), and wherein the semiconductor memory device (Figs. 1A, 1B) further comprises a separation spacer (items 341 plus 22 plus 321, item SP) interposed between an upper sidewall of the device isolation part (item 302) and a lower portion of the storage node contact (item BC).
In regards to claim 7, Kim (Figs. 1A, 1B and associated text) discloses wherein the separation spacer (items 341 plus 22 plus 321) includes: a first separation spacer (items 341 or 321) in contact with an upper sidewall of the device isolation part (item 302); and a second separation spacer (items 321 or 22) interposed between the first separation spacer (items 341 or 321) and a lower portion of the storage node contact (item BC), wherein the second separation spacer (items 321 or 22) includes a material different from a material of the first separation spacer (items 341 or 321, paragraphs 52, 53, 59).
In regards to claim 8, Kim (Figs. 1A, 1B and associated text) discloses wherein a lower portion (lower portion of item BC) of the storage node (item BC) contact has a first width (width of lower portion of item BC) in the first direction, and wherein an upper portion (upper portion of item BC) of the storage node contact (item BC) has a second width (width of upper portion of item BC) greater than the first width (width of lower portion of item BC) in the first direction.
In regards to claim 9, Kim (Figs. 1A, 1B and associated text) discloses a contact metal pattern (diffusion prevention pattern, not shown, paragraph 61) on the storage node contact (item BC); an ohmic pattern (mentioned, but not shown, paragraph 61) between the contact metal pattern (diffusion prevention pattern, not shown, paragraph 61) and the storage node contact (item BC); and a landing pad (item LP) on the contact metal pattern (diffusion prevention pattern, not shown, paragraph 61), wherein the lower sidewall of the storage node contact (item BC) is not vertically aligned with a sidewall of the ohmic pattern (mentioned, but not shown, paragraph 61).
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date to incorporate the teachings of Kim for the purpose of protection, isolation, an electrical connection and a memory device with improved reliability (paragraph 4).
In regards to claim 11, Huang (Fig. 2G and associated text) as modified by Kim (Figs. 1A, 1B and associated text) discloses further comprising: a second bit line (item 250 on the right, Huang) spaced apart from the first bit line (item 250 on the left, Huang) in the first direction, the storage node contact (item 272, Huang) interposed between the second bit line (item 250 on the right, Huang) and the first bit line (item 250 on the left, Huang); an interlayer insulating layer (item 262, Huang, items 22 or 321, Kim) interposed between the second bit line (item 250 on the right, Huang) and the device isolation part (item 240, Huang); and a separation spacer (items 341, 22 , 321, 341 plus 321 or 341 plus 22 plus 321, Kim) interposed between an upper sidewall of the device isolation part (item 240, Huang, item 302, Kim) and a lower portion of the storage node contact (item 272, Huang, item BC, Kim), wherein a lower surface of the separation spacer (items 341, 22 , 321, 341 plus 321 or 341 plus 22 plus 321, Kim) has a first level, and wherein a lower surface of the interlayer insulating layer (item 262, Huang, items 22 or 321, Kim) has a second level equal to or lower than the first level.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See All references listed in 892. Examiner suggests that the Applicant perfect their foreign priority as there are some references commonly assigned listed in the 892 and the provided IDS’s.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 February 22, 2026