DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4 and 6-11 have been considered but are moot on grounds of new rejection and interpretation of prior art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2017/0200724 A1 now US 9,704,872 B1) in view of Kim et al. (Kim’019) (KR 20220162019 A1).
In regards to claim 1, Huang (Fig. 2G and associated text) discloses a semiconductor memory device (item 200, Fig. 2G) comprising: a device isolation part (item 240) on a substrate (item 210), the device isolation part (item 240) defining a first active portion (item 222) and a second active portion (item 224), a center portion of the first active portion (item 222) adjacent in a first direction to an edge portion of the second active portion (item 224 [not shown if Figures, but implicitly disclosed since Huang discloses DRAM with buried word line architecture); a first impurity region (item 222) in the center portion of the first active portion; a second impurity region (item 224) in the edge portion of the second active portion; a first bit line (item 250) in direct contact with the first impurity region (item 222) and crossing the substrate (item 210) in a second direction, the second direction intersecting the first direction; and a storage node contact (item 272) in contact with the second impurity region (item 224), wherein an upper end of the first impurity region (item 222) is higher than an upper end of the second impurity region (item 224), and wherein an upper sidewall (upper inner sidewall) of the storage node contact (item 272) is not vertically aligned with a lower sidewall (lower inner sidewall) of the storage node contact (item 272), the upper sidewall (upper inner sidewall) and the lower sidewall (lower inner sidewall) both on a common side of the storage node contact (item 272), wherein the storage node contact (item 272) comprises an upper portion of the storage node (upper portion of item 272) contact and a lower portion of the storage node contact (lower portion of item 272), wherein the upper portion (upper portion of item 272) is offset from the lower portion lower portion of the storage node contact (lower portion of item 272). Examiner notes that the innermost sidewall of the upper portion of item 272 is laterally/horizontally offset from the innermost sidewall of the lower portion of item 272.
Huang does not specifically disclose wherein the upper end of the first impurity region is higher than the upper end of the device isolation part. Examiner notes than the Applicant has not given any criticality as to where this claimed relationship yields an unexpected result and/or advantage. Examiner takes the position that this recitation merely stems from the difference in the devices of the current prior art of record and the Applicant’s device, however there is no support within the specification. The Applicant’s specification leans more towards the height difference of the first and second impurity regions.
Kim’019 discloses wherein the upper end of the first impurity region (item 3d) is higher than the upper end of the device isolation part (item 302).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim’019 for the purpose of reducing contact resistance, improving operation speed and reduced power consumption.
In regards to claim 2, Huang (Fig. 2G and associated text) discloses further comprising: a second bit line (item 250 on the right) extending in the second direction and spaced apart from the first bit line (item 250 on the left) in the first direction, the storage node contact (item 272) interposed between the second bit line (item 250 on the right) and the first bit line (item 250 on the left); and a bit line spacer (item 252) interposed between the second bit line (item 250 on the right) and the storage node contact (item 272), wherein the lower portion of the storage node contact (item 272) is below the bit line spacer (item 252).
In regards to claim 3, Huang (Fig. 2G and associated text) discloses further comprising an interlayer insulating layer (item 262) interposed between the second bit line (item 250 on the right) and the device isolation part (item 240), wherein an upper portion of the interlayer insulating layer (items 258 plus 264) has a first width (width of item 258 plus 264), and wherein a lower portion of the interlayer insulating layer (items 262) has a second width smaller (width of item 262) than the first width (width of item 258 plus 264).
In regards to claim 10, Huang (Fig. 2G and associated text) discloses further comprising a bit line spacer (items 264 plus 258 plus 254) interposed between the first bit line (item 250 on the left) and the storage node contact (item 272), wherein the bit line spacer (items 264 plus 258 plus 254) includes first, second, and third sub-spacers (items 264, 258 and 254) sequentially on sidewalls of the first bit line (item 250 on the left), wherein lower portions of the first and second sub-spacers (item 268 and 258) extend across a lower surface of the third sub-spacer (item 254).
Claim(s) 4, 6-9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2017/0200724 A1 now US 9,704,872 B1) in view of Kim et al. (Kim) (KR 20220162019 A1) as applied to claims 1-3 and 10 above, and further in view of Kim et al. (Kim) (US 2021/0296237 A1 now US 11,600,570 B2).
In regards to claim 4, Huang as modified by Kim’019 does not specifically disclose wherein the common side of the storage node contact has an inflection point between the upper sidewall and the lower sidewall.
Kim (Fig. 1B and associated text) discloses wherein the common side of the storage node contact (item BC) has an inflection point (item PT1) between the upper sidewall (upper inner sidewall of item BC) and the lower sidewall (lower inner sidewall of item BC).
It would have been obvious to modify the invention to include a common side of the storage node contact having an inflection point between the upper sidewall and the lower sidewall, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 6, Kim (Figs. 1A, 1B and associated text) discloses wherein the device isolation part (item 302) is interposed between the first impurity region (item 312a) and the second impurity region (item 312b), and wherein the semiconductor memory device (Figs. 1A, 1B) further comprises a separation spacer (items 341 plus 22 plus 321, item SP) interposed between an upper sidewall of the device isolation part (item 302) and the lower portion of the storage node contact (item BC).
In regards to claim 7, Kim (Figs. 1A, 1B and associated text) discloses wherein the separation spacer (items 341 plus 22 plus 321) includes: a first separation spacer (items 341 or 321) in contact with an upper sidewall of the device isolation part (item 302); and a second separation spacer (items 321 or 22) interposed between the first separation spacer (items 341 or 321) and the lower portion of the storage node contact (item BC), wherein the second separation spacer (items 321 or 22) includes a material different from a material of the first separation spacer (items 341 or 321, paragraphs 52, 53, 59).
In regards to claim 8, Kim (Figs. 1A, 1B and associated text) discloses wherein the lower portion (lower portion of item BC) of the storage node (item BC) contact has a first width (width of lower portion of item BC) in the first direction, and wherein an upper portion (upper portion of item BC) of the storage node contact (item BC) has a second width (width of upper portion of item BC) greater than the first width (width of lower portion of item BC) in the first direction.
In regards to claim 9, Kim (Figs. 1A, 1B and associated text) discloses a contact metal pattern (diffusion prevention pattern, not shown, paragraph 61) on the storage node contact (item BC); an ohmic pattern (mentioned, but not shown, paragraph 61) between the contact metal pattern (diffusion prevention pattern, not shown, paragraph 61) and the storage node contact (item BC); and a landing pad (item LP) on the contact metal pattern (diffusion prevention pattern, not shown, paragraph 61), wherein the lower sidewall of the storage node contact (item BC) is not vertically aligned with a sidewall of the ohmic pattern (mentioned, but not shown, paragraph 61).
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date to incorporate the teachings of Kim for the purpose of protection, isolation, an electrical connection and a memory device with improved reliability (paragraph 4).
In regards to claim 11, Huang (Fig. 2G and associated text) as modified by Kim’019 and Kim (Figs. 1A, 1B and associated text) discloses further comprising: a second bit line (item 250 on the right, Huang) spaced apart from the first bit line (item 250 on the left, Huang) in the first direction, the storage node contact (item 272, Huang) interposed between the second bit line (item 250 on the right, Huang) and the first bit line (item 250 on the left, Huang); an interlayer insulating layer (item 262, Huang, items 22 or 321, Kim) interposed between the second bit line (item 250 on the right, Huang) and the device isolation part (item 240, Huang); and a separation spacer (items 341, 22 , 321, 341 plus 321 or 341 plus 22 plus 321, Kim) interposed between an upper sidewall of the device isolation part (item 240, Huang, item 302, Kim) and the lower portion of the storage node contact (item 272, Huang, item BC, Kim), wherein a lower surface of the separation spacer (items 341, 22 , 321, 341 plus 321 or 341 plus 22 plus 321, Kim) has a first level, and wherein a lower surface of the interlayer insulating layer (item 262, Huang, items 22 or 321, Kim) has a second level equal to or lower than the first level.
Claim(s) 1-4 and 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2017/0200724 A1 now US 9,704,872 B1) in view of Kim et al. (Kim’019) (KR 20220162019 A1) as evidenced by or in view of Kim et al. (Kim) (US 2021/0296237 A1 now US 11,600,570 B2) or KR 102238951 B1.
In regards to claim 1, Huang (Fig. 2G and associated text) discloses a semiconductor memory device (item 200, Fig. 2G) comprising: a device isolation part (item 240) on a substrate (item 210), the device isolation part (item 240) defining a first active portion (item 222) and a second active portion (item 224), a center portion of the first active portion (item 222) adjacent in a first direction to an edge portion of the second active portion (item 224 [not shown if Figures, but implicitly disclosed since Huang discloses DRAM with buried word line architecture); a first impurity region (item 222) in the center portion of the first active portion; a second impurity region (item 224) in the edge portion of the second active portion; a first bit line (item 250) in direct contact with the first impurity region (item 222) and crossing the substrate (item 210) in a second direction, the second direction intersecting the first direction; and a storage node contact (item 272) in contact with the second impurity region (item 224), wherein an upper end of the first impurity region (item 222) is higher than an upper end of the second impurity region (item 224), and wherein an upper sidewall (upper inner sidewall) of the storage node contact (item 272) is not vertically aligned with a lower sidewall (lower inner sidewall) of the storage node contact (item 272), the upper sidewall (upper inner sidewall) and the lower sidewall (lower inner sidewall) both on a common side of the storage node contact (item 272), wherein the storage node contact (item 272) comprises an upper portion of the storage node (upper portion of item 272) contact and a lower portion of the storage node contact (lower portion of item 272), wherein the upper portion (upper portion of item 272) is offset from the lower portion lower portion of the storage node contact (lower portion of item 272). Examiner notes that the innermost sidewall of the upper portion of item 272 is laterally/horizontally offset from the innermost sidewall of the lower portion of item 272.
Huang does not specifically disclose wherein the upper end of the first impurity region is higher than the upper end of the device isolation part. Examiner notes than the Applicant has not given any criticality as to where this claimed relationship yields an unexpected result and/or advantage. Examiner takes the position that this recitation merely stems from the difference in the devices of the current prior art of record and the Applicant’s device, however there is no support within the specification. The Applicant’s specification leans more towards the height difference of the first and second impurity regions.
Kim’019 discloses wherein the upper end of the first impurity region (item 3d) is higher than the upper end of the device isolation part (item 302).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim’019 for the purpose of reducing contact resistance, improving operation speed and reduced power consumption.
As evidenced by Kim (Figs. 1B, 19 and associated text and items) the storage node contact (item BC) can comprise an upper portion of the storage node contact (upper portion of item BC) and a lower portion of the storage node contact (lower portion of item BC), wherein the upper portion (upper portion of item BC) is offset from the lower portion lower portion of the storage node contact (lower portion of item BC).
As evidenced by KR 102238951 B1 (Figs. 2a, 2b, 4p, 6e, 8e and associated text and items) the storage node contact (item 117) can comprise an upper portion of the storage node contact (item 117A) and a lower portion of the storage node contact (item 117B), wherein the upper portion (item 117A) is offset from the lower portion lower portion of the storage node contact (item 117B).
Therefore it would have been obvious to one of ordinary skill in the art to incorporate the teachings of Kim or KR102238951 B1 for the purpose of increasing the contact area.
In regards to claim 2, Huang (Fig. 2G and associated text) discloses further comprising: a second bit line (item 250 on the right) extending in the second direction and spaced apart from the first bit line (item 250 on the left) in the first direction, the storage node contact (item 272) interposed between the second bit line (item 250 on the right) and the first bit line (item 250 on the left); and a bit line spacer (item 252) interposed between the second bit line (item 250 on the right) and the storage node contact (item 272), wherein the lower portion of the storage node contact (item 272) is below the bit line spacer (item 252).
In regards to claim 3, Huang (Fig. 2G and associated text) discloses further comprising an interlayer insulating layer (item 262) interposed between the second bit line (item 250 on the right) and the device isolation part (item 240), wherein an upper portion of the interlayer insulating layer (items 258 plus 264) has a first width (width of item 258 plus 264), and wherein a lower portion of the interlayer insulating layer (items 262) has a second width smaller (width of item 262) than the first width (width of item 258 plus 264).
In regards to claim 4, Huang as modified by Kim’019 does not specifically disclose wherein the common side of the storage node contact has an inflection point between the upper sidewall and the lower sidewall.
Kim (Fig. 1B and associated text) discloses wherein the common side of the storage node contact (item BC) has an inflection point (item PT1) between the upper sidewall (upper inner sidewall of item BC) and the lower sidewall (lower inner sidewall of item BC).
It would have been obvious to modify the invention to include a common side of the storage node contact having an inflection point between the upper sidewall and the lower sidewall, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 6, Kim (Figs. 1A, 1B and associated text) discloses wherein the device isolation part (item 302) is interposed between the first impurity region (item 312a) and the second impurity region (item 312b), and wherein the semiconductor memory device (Figs. 1A, 1B) further comprises a separation spacer (items 341 plus 22 plus 321, item SP) interposed between an upper sidewall of the device isolation part (item 302) and the lower portion of the storage node contact (item BC).
In regards to claim 7, Kim (Figs. 1A, 1B and associated text) discloses wherein the separation spacer (items 341 plus 22 plus 321) includes: a first separation spacer (items 341 or 321) in contact with an upper sidewall of the device isolation part (item 302); and a second separation spacer (items 321 or 22) interposed between the first separation spacer (items 341 or 321) and the lower portion of the storage node contact (item BC), wherein the second separation spacer (items 321 or 22) includes a material different from a material of the first separation spacer (items 341 or 321, paragraphs 52, 53, 59).
In regards to claim 8, Kim (Figs. 1A, 1B and associated text) discloses wherein the lower portion (lower portion of item BC) of the storage node (item BC) contact has a first width (width of lower portion of item BC) in the first direction, and wherein an upper portion (upper portion of item BC) of the storage node contact (item BC) has a second width (width of upper portion of item BC) greater than the first width (width of lower portion of item BC) in the first direction.
In regards to claim 9, Kim (Figs. 1A, 1B and associated text) discloses a contact metal pattern (diffusion prevention pattern, not shown, paragraph 61) on the storage node contact (item BC); an ohmic pattern (mentioned, but not shown, paragraph 61) between the contact metal pattern (diffusion prevention pattern, not shown, paragraph 61) and the storage node contact (item BC); and a landing pad (item LP) on the contact metal pattern (diffusion prevention pattern, not shown, paragraph 61), wherein the lower sidewall of the storage node contact (item BC) is not vertically aligned with a sidewall of the ohmic pattern (mentioned, but not shown, paragraph 61).
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date to incorporate the teachings of Kim for the purpose of protection, isolation, an electrical connection and a memory device with improved reliability (paragraph 4).
In regards to claim 10, Huang (Fig. 2G and associated text) discloses further comprising a bit line spacer (items 264 plus 258 plus 254) interposed between the first bit line (item 250 on the left) and the storage node contact (item 272), wherein the bit line spacer (items 264 plus 258 plus 254) includes first, second, and third sub-spacers (items 264, 258 and 254) sequentially on sidewalls of the first bit line (item 250 on the left), wherein lower portions of the first and second sub-spacers (item 268 and 258) extend across a lower surface of the third sub-spacer (item 254).
In regards to claim 11, Huang (Fig. 2G and associated text) as modified by Kim’019 and Kim (Figs. 1A, 1B and associated text) discloses further comprising: a second bit line (item 250 on the right, Huang) spaced apart from the first bit line (item 250 on the left, Huang) in the first direction, the storage node contact (item 272, Huang) interposed between the second bit line (item 250 on the right, Huang) and the first bit line (item 250 on the left, Huang); an interlayer insulating layer (item 262, Huang, items 22 or 321, Kim) interposed between the second bit line (item 250 on the right, Huang) and the device isolation part (item 240, Huang); and a separation spacer (items 341, 22 , 321, 341 plus 321 or 341 plus 22 plus 321, Kim) interposed between an upper sidewall of the device isolation part (item 240, Huang, item 302, Kim) and the lower portion of the storage node contact (item 272, Huang, item BC, Kim), wherein a lower surface of the separation spacer (items 341, 22 , 321, 341 plus 321 or 341 plus 22 plus 321, Kim) has a first level, and wherein a lower surface of the interlayer insulating layer (item 262, Huang, items 22 or 321, Kim) has a second level equal to or lower than the first level.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 June 30, 2026
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