Prosecution Insights
Last updated: May 29, 2026
Application No. 18/504,408

CREATING A SOLDER BARRIER BY CHANGING A MATERIAL PROPERTY OF A TRACE ON A PRINTED CIRCUIT BOARD

Non-Final OA §102§103
Filed
Nov 08, 2023
Examiner
AYCHILLHUM, ANDARGIE M
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sandsik Technologies Inc.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
905 granted / 1075 resolved
+16.2% vs TC avg
Moderate +15% lift
Without
With
+14.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
8 currently pending
Career history
1088
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
80.7%
+40.7% vs TC avg
§102
15.2%
-24.8% vs TC avg
§112
0.2%
-39.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1075 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Drawings Figures 1A and 1B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 5-10 and 12-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rendek, JR. et al. (US 2012/0182702 A1) in view of Yang (CN 218677626 U). Pertaining to claim 1, Rendek et al. discloses, A printed circuit board (PCB) (12, see fig. 2E), comprising: a connection area (14, see fig. 2E) for receiving an electronic component (22, see fig. 2E); a trace (14, see fig. 2E) extending from the connection area (14); and a portion of the trace (14), But, Rendek et al. does not explicitly teach a solder barrier provided on at least one of a portion of the connection area, the solder barrier being formed by changing a material property of the at least one of the portions of the connection area and the portion of the trace However, Yang teaches a solder barrier provided on at least one of a portion of the connection area, the solder barrier being formed by changing a material property of the at least one of the portions of the connection area and the portion of the trace, (see paragraph [0040]). Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide a solder barrier provided on at least one of a portion of the connection area, the solder barrier being formed by changing a material property of the at least one of the portions of the connection area and the portion of the trace in the device of Rendek et al. based on the teachings of Yang in order to provide precision, reliability, and manufacturing efficiency over traditional photolithography or mechanical methods Pertaining to claim 2, Rendek et al. discloses, wherein the solder barrier (16) is formed by a laser ablation process (see paragraph [0012]). Pertaining to claims, 3, 10 and 18, Rendek et al. discloses all claimed limitations except, wherein the solder barrier is formed by a laser oxidation process. However, Yang teaches wherein the solder barrier is formed by a laser oxidation process, (see paragraph [0040]). Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide wherein the solder barrier is formed by a laser oxidation process in the device of Rendek et al. based on the teachings of Yang in order to provide precision, reliability, and manufacturing efficiency over traditional photolithography or mechanical methods. Pertaining to claim 5, Rendek et al. discloses, wherein when the solder barrier (16) is provided on the portion of the trace (14), the portion of the trace (14) on which the solder barrier (16) is provided is proximate to the connection area (15). Pertaining to claim 6, Rendek et al. discloses, wherein the connection area (15) is a solder pad (see paragraph [0018]). Pertaining to claims 7, 15 and 20, Rendek et al. discloses all claimed limitations except, wherein a finish of at least one of the connection areas and the trace is selected from a group, comprising: organic surface protectant (OSP); immersion silver; immersion tin; electroless nickel immersion gold (ENIG); electroless nickel electroless palladium immersion gold (ENEPIG); and copper. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to wherein a finish of at least one of the connection area and the trace is selected from a group, comprising: organic surface protectant (OSP); immersion silver; immersion tin; electroless nickel immersion gold (ENIG); electroless nickel electroless palladium immersion gold (ENEPIG); and copper, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for intended use for the purpose of primarily focused on protecting copper from oxidation, ensuring high solderability, and maintaining planar surfaces for component assembly In re Leshin, 125 USPQ 416. Pertaining to claim 8, Rendek et al. discloses, an attachment means provided on a surface of the PCB (12), the attachment means for receiving an electronic component (22); a signal transmission/trace (14) means extending from the attachment means; and a solder barrier (16) means provided on at least one of a portion of the attachment means and a portion of the signaling means, the solder barrier (16) means being formed by changing a property of the at least one of the portion of the attachment means and the portion of the signal transmission means (see paragraph [0011]). Pertaining to claim 9, Rendek et al. discloses, wherein the solder barrier (16) is formed by a laser ablation process (see paragraph [0012]). Pertaining to claim 12, Rendek et al. discloses, wherein when the solder barrier (16) means is provided on the portion of the signal transmission means/trace, the portion of the signal transmission means on which the solder barrier (16) is provided is proximate to the attachment means (see paragraph [0011]). . Pertaining to claim 13, Rendek et al. discloses, wherein the connection area (15) is a solder pad (see paragraph [0018]). Pertaining to claim 14, Rendek et al. discloses, wherein the solder barrier (16) means is formed on portion of a perimeter of the attachment means (see paragraph [0011]). Pertaining to claim 16, Rendek et al. discloses, forming a trace (14) and a solder pad (15) on a top surface of a printed circuit board (PCB); (12) and forming a solder barrier (16) by altering a material property of a portion of at least one of the traces(14) and the solder pad (15), the solder barrier (16) being used in lieu of a solder mask (16) on the at least one of the trace (14) and the solder pad (15). However, Yang teaches a solder barrier provided on at least one of a portion of the connection area, the solder barrier being formed by changing a material property of the at least one of the portions of the connection area and the portion of the trace, (see paragraph [0040]). Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide a solder barrier provided on at least one of a portion of the connection area, the solder barrier being formed by changing a material property of the at least one of the portions of the connection area and the portion of the trace in the device of Rendek et al. based on the teachings of Yang in order to provide precision, reliability, and manufacturing efficiency over traditional photolithography or mechanical methods Pertaining to claim 17, Rendek et al. discloses, wherein the solder barrier (16) is formed by a laser ablation process (see paragraph [0012]). Pertaining to claim 19, Rendek et al. discloses, wherein the solder barrier(16) is formed on the trace (14) proximate to the solder pad (15). Claims 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Rendek, JR. et al. (US 2012/0182702 A1) in view Yang (CN 218677626 U) as applied to claim 1 above, and further in view of Harkness (US 201601743604 A1). Pertaining to claim 4, 11, Rendek et al. discloses all claimed limitations except, wherein the trace is a high-speed trace. However, Harkness et al. teaches wherein the trace is a high-speed trace, (Abstract). Therefore, At the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to provide wherein the trace is a high-speed trace in the device of Rendek et al. based on the teachings of Harkness et al. in order to provide . The primary advantage of using a properly designed high-speed trace is the ability to transmit large amounts of data at high frequencies (GHz range) without significant distortion, attenuation, or electromagnetic interference (EMI). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Heinz (US 200400484-A1) and Tuominen (US 20210202427-A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDARGIE M AYCHILLHUM whose telephone number is (571)270-1607. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDARGIE M AYCHILLHUM/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

Nov 08, 2023
Application Filed
Mar 24, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+14.8%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1075 resolved cases by this examiner. Grant probability derived from career allowance rate.

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