DETAILED ACTION
This correspondence is in response to the communications received November 8, 2023. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Relevant Prior Art
Chou (US 12,484,323) Fig. 21, shown below. Where the bond pads are 214/114.
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VGR (Sony) Endo et al. (US 2011/0155893) Fig. 1, shown below.
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Claim Objections
Claims 15 and 16 are objected to because of the following informalities: The recitation, “…shape when viewed in plan” should be corrected to read as “…shape view”. Appropriate correction is required.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 4, an image sensor, comprising:
a circuit chip (20, ¶ 0067); and
an image sensor chip (10) on the circuit chip (10 on 20),
wherein the image sensor chip (10) includes:
a first substrate (100) extending in a first direction and a second direction (X and Y horizontal directions);
a first interlayer dielectric layer (interpreted by construction of the claims, as the “first interlayer dielectric layer 810, second interlayer dielectric layer 820”, ¶ 0067) between the first substrate (100) and the circuit chip (20); and
a first bonding pad (850, ¶ 0067) in the first interlayer dielectric layer (in portion 820 of 810 and 820),
wherein the first bonding pad (850) has a first width in the first direction,
wherein the circuit chip (20) includes:
a second substrate (1000);
a second interlayer dielectric layer (1820) and a third interlayer dielectric layer (2820) that are sequentially stacked on the second substrate (shown); and
a second bonding pad (2850) in the second and third interlayer dielectric layers (in portion 2820 of 1820 and 2820),
wherein the second bonding pad (2850) has a second width in the first direction,
wherein the first and second bonding pads are in contact with each other (850 shown in contact with 2850), and
wherein a change in the second width along a third direction is greater than a change in the first width along the third direction, the third direction intersects the first direction and the second direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US 10,978,505) in view of Yang et al. (US 2024/0079434).
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Regarding claim 1, the prior art of Sato discloses in Fig. 28, an image sensor, comprising:
a circuit chip (“logic substrate LGC”, col. 6, lines 59, where transistors making up circuits in SSB and wirings in SML are clearly present, the “circuit” aspect therefore is satisfied. Then the “chip” aspect is satisfied by the recitation from col. 1, lines 39-45, where the diced wafers are diced into individual devices, which are known as “chips”, clearly referring to the same concept of die / diced wafer devices / chips, which are further described as “chips” in col. 12, lines 27-30); and
an image sensor chip (“sensor substrate SEN”, col. 6, line 39, wherein the “chip” aspect is satisfied by the discussion in col. 12, lines 27-30, “In this manner, the main part of the solid-state imaging device is formed. Subsequently, the wafer is diced along the dicing regions DIR to take out solid-state imaging devices in the form of chips.”) on the circuit chip (SEN on LGC),
wherein the image sensor chip (SEN) includes:
a first substrate (“first semiconductor substrate FSB”, col. 6, line 24) extending in a first direction and a second direction (FSB is a three dimensional object which has lateral dimensions into page and across page of Fig. 28);
a first interlayer dielectric layer (“first interconnect structure FML”, col. 6, line 29, where FML includes interlayer insulating films SI1 through SI5, see Fig. 15, col. 8, lines 41-42 for SI1, col. 8, lines 59-60 for SI2, col. 9, lines 1-2 for SI3, col. 9, lines 6-7 for SI4, col. 9, lines 20-21 for SI5) between the first substrate and the circuit chip (FML between FSB and LGC); and
a first bonding pad (“bonding pads SPD”, col. 6, lines 30-40) in the first interlayer dielectric layer (SPD in SI5 of FML),
wherein the first bonding pad has a first width in the first direction (SPD has a given width across page of Fig. 28), wherein the circuit chip (LGC) includes:
a second substrate (“second semiconductor substrate SSB”, col. 6, lines 40-41);
a second interlayer dielectric layer (portion of SML including interlayer dielectric layers of LI1 to LI4, of the “second interconnect structure SML”, see Fig. 24, col. 10, line 45 to col. 11, line 5) and a third interlayer dielectric layer (portion of SML including interlayer dielectric layer of LI5 of “second interconnect structure SML”, see Fig. 24, col. 11, lines 6-7) that are sequentially stacked on the second substrate (both portions of SML on SSB); and
a second bonding pad (“bonding pads LPD”, col. 6, line 54) in the … third interlayer dielectric layer (LPD in upper portion of SML),
wherein the second bonding pad (LPD) has a second width in the first direction (given width of LPD),
wherein the first and second bonding pads are in contact with each other (SPD and LPD are shown to be in direct contact with each other, col. 7, lines 57-65), and
a third direction (vertical direction), the third direction intersects the first direction and the second direction (vertical direction intersects the two horizontal directions of into page and across page directions).
Sato does not disclose,
“a second bonding pad in the second and third interlayer dielectric layers,
…
wherein a change in the second width along a third direction is greater than a change in the first width along the third direction”.
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First interpretation of Yang discloses in (annotated) Fig. 9E,
a second bonding pad (interpreted to be features topmost 114, 116, ¶ 0103-0104, which are made up of 902, 904. This interpretation is taken directly from Applicant’s Fig. 4, where the lower bond pad is made up of a wider part 2850 and a narrow part just below, where both parts make up the bond pad which is located within two distinct dielectric layers.) in the second [dielectric layer] (¶ 0102, dielectric layer portions of 906, 912, within the “imaging interconnect structure 110”, ¶ 0040) and third interlayer dielectric layers (¶ 0102, dielectric layer of 914, as annotated, within the “imaging interconnect structure 110”, ¶ 0040),
…
wherein a change in the second width along a third direction is greater than a change in the first width along the third direction (The “first bond pad” is interpreted to be 515. The “second bond pad” is interpreted to be 114, 116. Therefore, the change in width along the vertical direction of 114, 116 is shown to be greater than change in width of 515 along vertical direction).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a second bonding pad in the second and third interlayer dielectric layers,
…
wherein a change in the second width along a third direction is greater than a change in the first width along the third direction”, as disclosed by Yang in the system of Sato, for the purpose of a reduction of size of the interconnections for smaller devices in the logic substrate versus what is required for the relatively larger sized photoelectric conversion devices in the light sensor substrate. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
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Second interpretation of Yang discloses in Fig. 9A (with annotations by Examiner),
a second bonding pad (circled annotated as features 114, 116, 126, ¶ 0103-0104, which are made up of 902, 904. This interpretation is taken directly from Applicant’s Fig. 4, where the lower bond pad is made up of a wider part 2850 and a narrow part just below, where both parts make up the bond pad which is located within two distinct dielectric layers.) in the second [dielectric layer] (¶ 0102, dielectric layer portions of 906, 912, 914, within the “imaging interconnect structure 110”, ¶ 0040) and third interlayer dielectric layers (¶ 0102, dielectric layer of 912, 916, 914 in 118, within the “imaging interconnect structure 118”, ¶ 0040),
…
wherein a change in the second width along a third direction is greater than a change in the first width along the third direction (The “first bond pad” is interpreted to be 515, 514. The “second bond pad” is interpreted to be 114, 116, 126. Therefore, the change in width along the vertical direction of 114, 116, 126 is shown to be greater than change in width of 515, 514 along vertical direction).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a second bonding pad in the second and third interlayer dielectric layers,
…
wherein a change in the second width along a third direction is greater than a change in the first width along the third direction”, as disclosed by Yang in the system of Sato, for the purpose of a reduction of size of the interconnections for smaller devices in the logic substrate versus what is required for the relatively larger sized photoelectric conversion devices in the light sensor substrate, or for the purpose of allowing for any alignment mismatch to reduce alignment connection error. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
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Third interpretation of Yang discloses in Fig. 9F (with annotations by Examiner),
a second bonding pad (annotated “second bonding pad”, ¶ 0103-0104, which are made up of 902, 904. This interpretation is taken directly from Applicant’s Fig. 4, where the lower bond pad is made up of a wider part 2850 and a narrow part just below, where both parts make up the bond pad which is located within two distinct dielectric layers.) in the second [dielectric layer] (¶ 0102, dielectric layer portions of 906, 912, annotated “second dielectric layer”, within the “imaging interconnect structure 110”, ¶ 0040) and third interlayer dielectric layers (¶ 0102, dielectric layer of 914 in 118, annotated “third dielectric layer”, within the “imaging interconnect structure 110”, ¶ 0040),
…
wherein a change in the second width along a third direction is greater than a change in the first width along the third direction (The annotated “first bonding pad” is interpreted to be 514. The annotated “second bonding pad” is interpreted to be 114, 116. Therefore, the change in width along the vertical direction of 114, 116 is shown to be greater than change in width of 514 along vertical direction).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a second bonding pad in the second and third interlayer dielectric layers,
…
wherein a change in the second width along a third direction is greater than a change in the first width along the third direction”, as disclosed by Yang in the system of Sato, for the purpose of allowing for any alignment mismatch to reduce alignment connection error. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Sato et al. disclose the image sensor of claim 1, and in the combination rejection under Yang, Fig. 9A or 9E discloses, wherein the second width is constant or increases along the third direction (the width of 114, 116 is both constant at portions and the width over the entire vertical dimension, increases from the lower positions to higher positions).
Regarding claim 3, the prior art of Sato et al. disclose the image sensor of claim 1, and in the combination rejection under Yang, Fig. 9A discloses, wherein the first width (width of 515) gradually decreases along the third direction (when moving up through vertical positions, the width of 515 to 514 decreases).
Regarding claim 4, the prior art of Sato et al. disclose the image sensor of claim 1, and in the combination rejection under Yang, Fig. 9A discloses,
wherein the first bonding pad (514, 515) includes:
a first metal pattern (904, ¶ 0103, 0104); and
a first barrier pattern (in region of 514, 515, layer 902, ¶ 0103 discloses the material to be metal nitrides, which the Applicant’s own disclosure interpreted as being a barrier material, see Applicant’s ¶ 0072, see note below) on a top surface and lateral surfaces of the first metal pattern (in region with 514/515 902 covers top and side surfaces of 904),
wherein the second bonding pad (114, 116, 126) includes:
a second barrier pattern (in region of 114, 116, 126… layer 902, ¶ 0103 discloses the material to be metal nitrides, which the Applicant’s own disclosure interpreted as being a barrier material, see Applicant’s ¶ 0072, see note below); and
a second metal pattern (in region of 114, 116, 126, portion 904, ¶ 0103, “The conductive body 904 may, for example, be or comprise copper, aluminum, tungsten, ruthenium, another conductive material, or any combination of the foregoing.”) on the second barrier pattern (904 on 902),
wherein the first and second metal patterns include copper, aluminum, tungsten, molybdenum, or a combination thereof (both portions 904, ¶ 0103, “The conductive body 904 may, for example, be or comprise copper, aluminum, tungsten, ruthenium, another conductive material, or any combination of the foregoing.”).
Note: It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the barrier pattern of Yang would inherently have the property of a being a barrier, because the material for 902 is a metal nitride (see ¶ 0103, “The conductive liner 902 may, for example, be or comprise titanium nitride, tantalum nitride, or the like”), which is the same as the barrier material as disclosed (see ¶ 0072, “The first conductive pattern 911 may serve as a barrier layer or an adhesive layer. The first conductive pattern 911 may include one or more of metal and metal nitride.”). See MPEP 2112.01.
Regarding claim 5, the prior art of Sato et al. disclose the image sensor of claim 1, and in the combination rejection under Yang, Fig. 9E discloses, wherein a bottom surface of the first bonding pad is in contact with a top surface of the second bonding pad (bottom surface of 515 is in contact with top surface of topmost 116, 114), and a third width in the first direction of the bottom surface of the first bonding pad is greater than a fourth width in the first direction of the top surface of the second bonding pad (bottom width of 515 is wider than top surface of top most 116).
Regarding claim 6, the prior art of Sato et al. disclose the image sensor of claim 5, and in the combination rejection under Yang, Fig. 9E discloses, wherein the top surface of the second bonding pad is in contact with the first metal pattern and is not in contact with the first barrier pattern (in Yang Fig. 9E, the top surface of “second bonding pad”, which is 904 of 116, is not in contact with the “first bonding pad” 902).
Regarding claim 7, the prior art of Sato et al. disclose the image sensor of claim 6, and in the combination rejection under Yang, Fig. 9E discloses, wherein a portion of the bottom surface (bottom surface of the “first bonding pad” 515) is in contact with a top surface of the third interlayer dielectric layer (in contact with top surface of “third dielectric layer” 914).
Regarding claim 8, the prior art of Sato et al. disclose the image sensor of claim 1, and in the combination rejection under Yang, Fig. 9F discloses, wherein a bottom surface of the first bonding pad is in contact with a top surface of the second bonding pad (the annotated “first bonding pad” lower surface is in contact with the top surface of annotated “second bonding pad”), and a third width in the first direction of the bottom surface of the first bonding pad is less than a fourth width in the first direction of the top surface of the second bonding pad (the width of the annotated “first bonding pad” is less than the width the top surface of annotated “second bonding pad”).
Regarding claim 9, the prior art of Sato et al. disclose the image sensor of claim 8, and in the combination rejection under Yang, Fig. 9F discloses, wherein the bottom surface of the first bonding pad is in contact with the second metal pattern and is not in contact with the second barrier pattern (bottom surface of annotated “first bonding pad” is not in contact with the 902 portion of the annotated “second bonding pad”).
Regarding claim 10, the prior art of Sato et al. disclose the image sensor of claim 9, and in the combination rejection under Yang, Fig. 9F discloses, wherein a portion of the top surface of the second bonding pad is in contact with a bottom surface of the first interlayer dielectric layer (top surface of the “second bonding pad” is in contact with the 918 portion of the “first interlayer dielectric”).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US 10,978,505) in view of Yang et al. (US 2024/0079434) in view of Kuo et al. (US 11,075,242).
Regarding claim 11, the prior art of Sato et al. disclose the image sensor of claim 1, and Sato discloses in Fig. 28,
wherein the first substrate (FSB) has a first surface (upper surface of FSB) and a second surface (lower surface of FSB) that are opposite to each other and includes a photoelectric conversion area (PD),
wherein the pixel region (SRE) includes:
a transistor (discussed in col. 8, lines 32-40) on the second surface (on lower surface of FSB, the transistors shown made up of gate TGE, floating diffusion region FDR and diffusion PR).
Sato, however fails to disclose the configuration of,
“wherein the image sensor chip further includes a separation pattern in the first substrate, the separation pattern defining a pixel region, and
wherein the pixel region includes:
a device isolation pattern that defines an active area adjacent to the second surface in the pixel region”.
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Kuo discloses in Fig. 4,
wherein the image sensor chip further includes a separation pattern (136, col. 8, lines 55-60 state that the purpose of 136 are to be reflective elements, which isolate the incoming radiation to only impinge upon incoming surface of each pixel, and isolate incoming light to each pixel, also including materials of 304, which are dielectrics, see col. 12, lines 18-32) in the first substrate (equivalent substrate being “substrate 102”, col. 8, line 52),
the separation pattern (136/304) defining a pixel region (136/304 separate each pixel from each other, 104a, 104b), and
wherein the pixel region (104a, 104b) includes:
a device isolation pattern (110, col. 3, lines 31-45) that defines an active area (area of 102 not at 110, in each pixel) adjacent to the second surface in the pixel region (lower surface of 102).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the image sensor chip further includes a separation pattern in the first substrate, the separation pattern defining a pixel region, and
wherein the pixel region includes:
a device isolation pattern that defines an active area adjacent to the second surface in the pixel region”, as disclosed by Lin in the system of Sato, for the purpose isolating each pixel from a neighboring pixel, so as to improve the resolution of the captured image. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US 10,978,505) in view of Yang et al. (US 2024/0079434) in view of Kuo et al. (US 11,075,242) in view of Chen et al. (US 12,490,537).
Regarding claim 12, the prior art of Sato et al. disclose the image sensor of claim 11, and Sato discloses in Fig. 28,
wherein the image sensor chip (SEN) further includes the active area (region within each pixel in SRE) includes a floating diffusion area (FDR, col. 8, lines 32-40) adjacent to the gate pattern (adjacent to TGE).
Sato however, fails to disclose,
“wherein the image sensor chip further includes a buried gate pattern on the active area,
…
wherein the buried gate pattern extends in the first substrate.”
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Chen discloses in Fig. 8,
wherein the image sensor chip further includes a buried gate pattern (“transfer gate 114”, col. 15, line 54) on the active area (active portions of pixel in 102),
…
wherein the buried gate pattern (114) extends in the first substrate (114 extends into 102).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the image sensor chip further includes a buried gate pattern on the active area,
…
wherein the buried gate pattern extends in the first substrate.”, as disclosed by Chen in the system of Sato, for the purpose reducing the leakage current and improving resolution between light capture events. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 13, the prior art of Sato et al. disclose the image sensor of claim 12, and Sato discloses in Fig. 28, wherein the image sensor chip (SEN) further includes:
a plurality of color filters (CFL) on the first surface (top surface) of the first substrate (FSB); and
a plurality of microlenses (MLE) on the color filters (on CFL).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US 10,978,505) in view of Jang et al. (US 12,142,588).
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Regarding claim 14, the prior art of Sato discloses in Fig. 28, an image sensor (see title, “Solid-state Imaging Device Including A Sensor Substrate And A Logic Substrate”), comprising:
a circuit chip (“logic substrate LGC”, col. 6, lines 59, where transistors making up circuits in SSB and wirings in SML are clearly present, the “circuit” aspect therefore is satisfied. Then the “chip” aspect is satisfied by the recitation from col. 1, lines 39-45, where the diced wafers are diced into individual devices, which are known as “chips”, clearly referring to the same concept of die / diced wafer devices / chips, which are further described as “chips” in col. 12, lines 27-30); and
an image sensor chip (“sensor substrate SEN”, col. 6, line 39, wherein the “chip” aspect is satisfied by the discussion in col. 12, lines 27-30, “In this manner, the main part of the solid-state imaging device is formed. Subsequently, the wafer is diced along the dicing regions DIR to take out solid-state imaging devices in the form of chips.”) on the circuit chip (SEN on LGC),
wherein the image sensor chip (SEN) includes:
a first substrate (“first semiconductor substrate FSB”, col. 6, line 24) extending in a first direction and a second direction (FSB is a three dimensional object which has lateral dimensions into page and across page of Fig. 28);
a first interlayer dielectric layer (“first interconnect structure FML”, col. 6, line 29, where FML includes interlayer insulating films SI1 through SI5, see Fig. 15, col. 8, lines 41-42 for SI1, col. 8, lines 59-60 for SI2, col. 9, lines 1-2 for SI3, col. 9, lines 6-7 for SI4, col. 9, lines 20-21 for SI5) between the first substrate and the circuit chip (FML between FSB and LGC); and
a first bonding pad (“bonding pads SPD”, col. 6, lines 30-40) in the first interlayer dielectric layer (SPD in FML),
wherein the circuit chip (LGC) includes:
a second substrate (“second semiconductor substrate SSB”, col. 6, lines 40-41);
a second interlayer dielectric layer (portion LI5 of dielectric layers of LI1 to LI5, of the “second interconnect structure SML”, see Fig. 24, col. 10, line 45 to col. 11, line 7) on the second substrate (SML on SSB); and
a second bonding pad (“bonding pads LPD”, col. 6, line 54) in the second interlayer dielectric layer (LPD in upper portion of SML),
wherein the first and second bonding pads are in contact with each other (SPD and LPD shown in contact with each other, col. 7, lines 57-65).
Sato does not disclose,
“wherein a plurality of voids are included between the first and second bonding pads that are in contact with each other.”
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Jang discloses in Fig. 9A, wherein the bond pad junction has voids ‘V’ between contact structures (col. 13, lines 64-62, “Referring to FIG. 9A, a semiconductor device may be similar to the embodiment shown in FIG. 7, except for the misalignment with the first semiconductor chip 100 while the void V is present in the bonding structure of the second semiconductor chip 200. In addition, the elements of the embodiment of FIG. 9A may be understood with reference to the description of the same or similar elements of the embodiment shown in FIG. 7 unless specifically stated otherwise.”). In the alternative Jang shows in Fig. 12C, wherein filled voids 231’F are present in plurality between the bond pads (col. 17, lines 10-47).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein a plurality of voids are included between the first and second bonding pads that are in contact with each other.”, as disclosed by Jang in the system of Sato, for the purpose of improving bonding strength between the bonding pads (col. 14, lines 12-17). (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US 10,978,505) in view of Jang et al. (US 12,142,588) in view of Yang et al. (US 2024/0079434).
Regarding claim 15, the prior art of Sato et al. disclose the image sensor of claim 14, however Sato does not disclose,
“wherein a bottom surface of the first bonding pad and a top surface of the second bonding pad have a circular shape when viewed in plan, and a diameter of the bottom surface of the first bonding pad is different from a diameter of the top surface of the second bonding pad.”
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Yang discloses in Figs. 8B and 8C, wherein an upper “first bonding pad” (515a) and a lower “second bonding pad” (125a) are shown in direct contact with different widths and 125a has a plan view shape that is circular (shown in Fig. 8C).
With respect to the limitation “wherein a bottom surface of the first bonding … have a circular shape when viewed in plan”, it would have been obvious to one of ordinary skill in the art at the time the invention was made to select the plan view shape of the “first bonding pad” to be circular, since it was well known in the art that circular vertical electrical connections are efficient shapes for passing electrical signals effectively. Using a circular shaped vertical electrical connection is a common practice in the art because the circular shape is efficient for passing electrical signals effectively. Further, “[c]ommon sense teaches, however, that familiar items may have obvious uses beyond their primary purposes, and in many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” KSR Int’l Co. v. Teleflex Inc. 550 U.S.__, 82 USPQ2d 1385 (Supreme Court 2007).
E. KSR rational E obvious to try choosing from finite solutions with reasonable expectation of success
(1) a finding that at the time of the invention, there had been a recognized problem or need in the art, which may include a design need or market pressure to solve a problem;
(2) a finding that there had been a finite number of identified, predictable potential solutions to the recognized need or problem;
(3) a finding that one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Therefore the claim limitation would have been obvious to a person of ordinary skill in the art, as they would have good reason to pursue the known options (e.g. circular, square, or rectangular shaped) that would have been within their technical grasp.
Regarding claim 16, the prior art of Sato et al. disclose the image sensor of claim 14, however Sato does not disclose,
“wherein a bottom surface of the first bonding pad and a top surface of the second bonding pad have a square shape when viewed in plan, and a diagonal length of the bottom surface of the first bonding pad is different from a diagonal length of the top surface of the second bonding pad.”
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Yang discloses in Figs. 8B and 8D, wherein an upper “first bonding pad” (515a) and a lower “second bonding pad” (125a) are shown in direct contact with different widths and 125a has a plan view shape that is square shaped (shown in Fig. 8D). Further, a diagonal length of the bottom surface of the first bonding pad is different from a diagonal length of the top surface of the second bonding pad is satisfied as an upper “first bonding pad” (515a) and a lower “second bonding pad” (125a) are shown to have different diagonal lengths as they are differently sized.
With respect to the limitation “wherein a bottom surface of the first bonding pad … have a square shape when viewed in plan”, it would have been obvious to one of ordinary skill in the art at the time the invention was made to select the plan view shape of the “first bonding pad” to be square shaped, since it was well known in the art that square shaped vertical electrical connections are efficient shapes for passing electrical signals effectively. Using a square shaped vertical electrical connection is a common practice in the art because the square shaped is efficient for passing electrical signals effectively. Further, “[c]ommon sense teaches, however, that familiar items may have obvious uses beyond their primary purposes, and in many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” KSR Int’l Co. v. Teleflex Inc. 550 U.S.__, 82 USPQ2d 1385 (Supreme Court 2007).
E. KSR rational E obvious to try choosing from finite solutions with reasonable expectation of success
(1) a finding that at the time of the invention, there had been a recognized problem or need in the art, which may include a design need or market pressure to solve a problem;
(2) a finding that there had been a finite number of identified, predictable potential solutions to the recognized need or problem;
(3) a finding that one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Therefore the claim limitation would have been obvious to a person of ordinary skill in the art, as they would have good reason to pursue the known options (e.g. circular, square, or rectangular shaped) that would have been within their technical grasp.
Regarding claim 17, the prior art of Sato et al. disclose the image sensor of claim 14, and Sato discloses in Fig. 28, wherein the circuit chip (LGC) further includes an interlayer dielectric layer (as can be seen in Fig. 24, LI1 to LI4) between the second substrate (SSB) and the second interlayer dielectric layer (portion LI5),
wherein the second bonding pad (LPH) includes a via part (plural via parts shown in Fig. 28 emanating from LPH) that protrudes toward the interlayer dielectric layer (the via parts extending towards LI1 to LI4).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Sato et al. (US 10,978,505) in view of Tange et al. (US 2021/0313369) in view of Chen et al. (US 12,490,537) in view of Yang et al. (US 2024/0079434).
Regarding claim 18, the prior art of Sato discloses in Fig. 28, an image sensor (see title, “Solid-state Imaging Device Including A Sensor Substrate And A Logic Substrate”), comprising:
a circuit chip (“logic substrate LGC”, col. 6, lines 59, where transistors making up circuits in SSB and wirings in SML are clearly present, the “circuit” aspect therefore is satisfied. Then the “chip” aspect is satisfied by the recitation from col. 1, lines 39-45, where the diced wafers are diced into individual devices, which are known as “chips”, clearly referring to the same concept of die / diced wafer devices / chips, which are further described as “chips” in col. 12, lines 27-30); and
an image sensor chip (“sensor substrate SEN”, col. 6, line 39, wherein the “chip” aspect is satisfied by the discussion in col. 12, lines 27-30, “In this manner, the main part of the solid-state imaging device is formed. Subsequently, the wafer is diced along the dicing regions DIR to take out solid-state imaging devices in the form of chips.”) on the circuit chip (SEN on LGC),
wherein the image sensor chip (SEN) includes:
a first substrate (“first semiconductor substrate FSB”, col. 6, line 24) that has a first surface (top surface) and a second surface (lower surface) that are opposite to each other (shown) and photoelectric conversion areas (PD, “photodiodes PD (photoelectric conversion units)”, col. 6, line 28),
wherein the first substrate (FSB) includes a pixel region (“sensor region SRE”, col. 12, line 24, which includes pixels which each include PD);
a dielectric layer (“silicon oxide film SOF”, col. 12, lines 19-25) that covers the first surface (covers top surface of FSB);
a plurality of color filters (“color filters CFL” , col. 12, lines 19-25) on the dielectric layer (on SOF);
a protective layer (“silicon nitride film SNF” , col. 12, lines 19-25) between the dielectric layer (SOF) and the color filters (CFL);
a plurality of microlenses (“microlenses MLE” , col. 12, lines 19-25) on corresponding color filters (on CRL);
a gate pattern (“gate electrodes TGE”, col. 8, line 27) on the second surface (on lower surface of FSB);
a first wiring layer (portions SM1/SM3 of SM1/SM3/SM5, Fig. 11) on the gate pattern (shown indirectly ‘on’ TGE); and
a first bonding pad (“bonding pads SPD”, col. 9, line 23) between the first wiring layer (SM1/SM3/SM5) and the circuit chip (LGC),
wherein the circuit chip (LGC) includes:
a second substrate (“second semiconductor substrate SSB”, col. 6, line 41) on which integrated circuits are provided (several transistors shown integrated upon upper surface of SSB);
a second wiring layer (“second interconnect structure SML”, col. 6, line 49) on the second substrate (on SSB); and
a second bonding pad (“bonding pads LPD”, col. 6, lines 54-55) between the second wiring layer (SML) and the image sensor chip (SEN),
wherein the first wiring layer (FML) and the second wiring layer (SML) face each other and are electrically connected through the first and second bonding pads (FML and SML face each other and are connected through SPD/LPD),
wherein the first and second bonding pads are bonded to each other (SPD and LPD are bonded directly to each other, col. 7, lines 57-65),
wherein the first bonding pad (SPD) has a first sidewall and a second sidewall that are opposite to each other, the first sidewall having a negative slope, and the second sidewall having a positive slope (this is understood to mean and Sato discloses, that the opposing sidewalls of SPD have opposite inclined angles),
wherein the second bonding pad has a third sidewall and a fourth sidewall that are opposite to each other (LPD has opposing sidewalls that are opposite to each other).
First, Sato does not disclose, “wherein the first substrate includes … an optical black region”.
Tange discloses that the light shield (50, ¶ 0021) creates both a optical black region (“optical black (OB) pixels”, ¶ 0017), but that the light shield itself is an optical black component in the light receiving pixels, see ¶ 0017 and Fig. 3. Sato shows light shield features (MGD in Fig. 28) in the pixel regions, which define in part the pixel regions.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“wherein the first substrate includes … an optical black region”, as disclosed by Tange in the system of Sato, for the purpose of improving image resolution by preventing light cross talk between neighboring photoelectric capturing pixels. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Secondly, Sato does not disclose,
“a separation pattern that defines the photoelectric conversion areas in the first substrate;
a device isolation pattern adjacent to the second surface, the device isolation pattern defining an active area;
a buried gate pattern on the second surface”.
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Kuo discloses in Fig. 4,
“a separation pattern (136, col. 8, lines 55-60 state that the purpose of 136 are to be reflective elements, which isolate the incoming radiation to only impinge upon incoming surface of each pixel, and isolate incoming light to each pixel, also including materials of 304, which are dielectrics, see col. 12, lines 18-32) that defines the photoelectric conversion areas in the first substrate (136 delineates each pixel and it’s “photodiode 406”, col. 8, line 18);
a device isolation pattern (110, col. 3, lines 31-45) adjacent to the second surface (on lower surface of substrate 102),
the device isolation pattern (110) defining an active area (110 defines active area of 102, which is not at 110, in each pixel)”.
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Chen discloses in Fig. 8,
a buried gate pattern (“transfer gate 114”, col. 15, line 54) on the second surface (lower surface of substrate 102).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a separation pattern that defines the photoelectric conversion areas in the first substrate;
a device isolation pattern adjacent to the second surface, the device isolation pattern defining an active area;
a buried gate pattern on the second surface”, as disclosed by Kuo and Chen in the system of Sato, for the purpose isolating each pixel from a neighboring pixel, so as to improve the resolution of the captured image. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Third, Sato does not disclose, “[of the “second bonding pad”] wherein each of the third and fourth sidewalls has a stepped structure.”
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Yang discloses in Fig. 9A or 9B (with annotations by Examiner),
[of the annotated “second bond pad”] wherein each of the third and fourth sidewalls has a stepped structure (the sidewalls of “second bond pad” are shown to have a stepped structure, where the “second bond pad” is made from the circled annotation, as features 114, 116, 126, ¶ 0103-0104, which are made up of metal layers 902, 904).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“[of the annotated “second bond pad”] wherein each of the third and fourth sidewalls has a stepped structure”, as disclosed by Yang in the system of Sato, for the purpose of a reduction of size of the interconnections for smaller devices in the logic substrate versus what is required for the relatively larger sized photoelectric conversion devices in the light sensor substrate, or for the purpose of allowing for any alignment mismatch to reduce alignment connection error. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 19, the prior art of Sato et al. disclose the image sensor of claim 18, wherein a bottom surface of the first bonding pad is in contact with a top surface of the second bonding pad (Sato discloses in Fig. 28, SPD and LPD are bonded directly to each other, col. 7, lines 57-65), and Yang discloses in Fig. 9A and 9B (as disclosed in the rejection of claim 18) the bottom surface of the first bonding pad (bottom surface of annotated “first bond pad”) and the top surface of the second bonding pad (top surface of annotated “second bond pad”) have the same width (top and bottom bond pads have the same width as shown in Figs. 9A or 9B).
With respect to the limitation “the bottom surface of the first bonding pad and the top surface of the second bonding pad have the same area”, it would have been obvious to one of ordinary skill in the art at the time the invention was made to have the area of the mating surface of the bond pads be of the same area, since minimizing the size of all features can realize a higher device density per unit area. Using this configuration is common practice in the art because the equally sized areas with diminutive feature sizes can allow for higher device density per unit area. Further, “[c]ommon sense teaches, however, that familiar items may have obvious uses beyond their primary purposes, and in many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” KSR Int’l Co. v. Teleflex Inc. 550 U.S.__, 82 USPQ2d 1385 (Supreme Court 2007).
E. KSR rational E obvious to try choosing from finite solutions with reasonable expectation of success
(1) a finding that at the time of the invention, there had been a recognized problem or need in the art, which may include a design need or market pressure to solve a problem;
(2) a finding that there had been a finite number of identified, predictable potential solutions to the recognized need or problem;
(3) a finding that one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Therefore the claim limitation would have been obvious to a person of ordinary skill in the art, as they would have good reason to pursue the known options of minimizing device feature sizes to increase device density per unit area, which would have been within their technical grasp.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
“20. The image sensor of claim 18,
wherein a bottom surface of the first bonding pad is in contact with a top surface of the second bonding pad, the bottom surface of the first bonding pad and the top surface of the second bonding pad have different shapes from each other when viewed in plan, the bottom surface of the first bonding pad has a circular or tetragonal shape, and the top surface has a tetragonal or circular shape.”
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893