DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondo et al. U.S. Patent Publication No. 2008/0018761 (hereinafter Kondo) in view of Chang et al. U.S. Patent Publication No. 2020/0342196 (hereinafter Chang).
Consider claim 1, Kondo teaches an input sensing device comprising: a plurality of sensor pixels ([0046], pixel array) connected to a reset control line (Figure 7b, 111 or RSi), wherein each sensor pixel of the plurality of sensor pixels is connected to one of a plurality of driving lines (Figure 7b, 113 or SELi); a reset circuit configured to apply a reset signal through reset control lines connected to each of the plurality of sensor pixels (Figures 7b and 8, RS1-RSm); and a horizontal driver configured to sequentially apply a horizontal driving signal to the sensor pixels through the driving lines (Figure 7b and 8, SEL1-SELm), wherein the reset circuit simultaneously applies a reset signal to the plurality of sensor pixels (Figure 8, concurrent reset all pixels).
Kondo does not appear to specifically disclose wherein at least one of the plurality of sensor pixels further comprises: a first transistor including a first electrode connected to a reset voltage power line, a second electrode connected to a first node, and a gate electrode connected to one of the reset control lines; a photodiode including an anode electrode connected to a bias voltage power line and a cathode electrode directly connected to the first node, wherein a constant bias voltage is applied to the bias voltage power line; a second transistor including a first electrode connected to a common voltage power line and a gate electrode connected to the first node, wherein the common voltage power line is different from the reset voltage power line, and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another; and a third transistor including a first electrode connected to a second node, a second electrode connected to a signal input line, and a gate electrode connected to a corresponding one of the driving lines, wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor, wherein, during a sensing period within the single frame period, a gate- on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor, and wherein the reset period and the sensing period are not overlapped.
However, in a related field of endeavor, Chang teaches a sensing pixel in figure 3 and further teaches and further teaches wherein at least one of the plurality of sensor pixels further comprises: a first transistor including a first electrode connected to a reset voltage power line, a second electrode connected to a first node, and a gate electrode connected to one of the reset control lines (Figure 3, T1 and respective connections); a photodiode including an anode electrode connected to a bias voltage power line and a cathode electrode directly connected to the first node (Figure 3, PD and respective connections), wherein a constant bias voltage is applied to the bias voltage power line ([0040] refers to pulse and thus pulse has constant bias voltage during a period of time); a second transistor including a first electrode connected to a common voltage power line and a gate electrode connected to the first node (Figure 3, T2 and respective connections), wherein the common voltage power line is different from the reset voltage power line (Figures 3-4, SVSS and SVDD), and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another (Figures 3-4, SVSS and SVDD); and a third transistor including a first electrode connected to a second node, a second electrode connected to a signal input line, and a gate electrode connected to a corresponding one of the driving lines (Figure 3, T3 and respective connections), wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor (Figures 3-4, R_SW1), wherein, during a sensing period within the single frame period, a gate- on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor (Figures 3-4, R_SW3), and wherein the reset period and the sensing period are not overlapped ([0032], The transistor T1 may be served as a reset transistor, for resetting the voltage at the node N2 (i.e., reset the electric charges stored in the storage capacitor SC) before the exposure operation. The transistor T2 may be served as a source follower, for forwarding the electronic signal sensed by the optoelectronic element PD and stored in the storage capacitor SC to the sensing line C_SEN after the exposure operation is complete. The transistor T3 may be served as a select transistor, which may be turned on by the corresponding control signal when this pixel is selected (see also figure 6, Reset, exposure and Readout).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a sensing pixel as shown in figures 3-4 with the benefit that the fingerprint sensing pixel, which is configured to realize an optical fingerprint sensor. In addition, three row control signals are sent to the pixel through control signal lines R_SW1-R_SW3, respectively, allowing the pixel to output a sensing signal through a sensing line C_SEN (see [0031]).
Consider claim 2, Kondo and Chang teach all the limitations of claim 1. In addition, Kondo teaches wherein the reset circuit applies the reset signal to the plurality of sensor pixels a plurality of times (Figure 9, plurality of times for RS1-RSm) before applying the horizontal driving signal to the sensor pixels (Figure 9, before SEL1-SELm).
Consider claim 7, Kondo teaches an input sensing device comprising: a plurality of sensor pixels ([0046], pixel array) connected to a reset control line (Figure 7b, 111 or RSi), wherein each sensor pixel of the plurality of sensor pixels is connected to one of a plurality of driving lines (Figure 7b, 113 or SELi); a reset circuit configured to apply a reset signal through reset control lines connected to each of the plurality of sensor pixels (Figures 7b and 8, RS1-RSm); and a horizontal driver configured to sequentially apply a horizontal driving signal to the sensor pixels through the driving lines (Figure 7b and 8, SEL1-SELm), wherein the reset circuit simultaneously applies a reset signal to the plurality of sensor pixels (Figure 8, concurrent reset all pixels).
Kondo does not appear to specifically disclose a display device comprising an input sensing device; wherein at least one of the plurality of sensor pixels further comprises: a first transistor including a first electrode connected to a reset voltage power line, a second electrode connected to a first node, and a gate electrode connected to one of the reset control lines; a photodiode including an anode electrode connected to a bias voltage power line and a cathode electrode directly connected to the first node, wherein a constant bias voltage is applied to the bias voltage power line; a second transistor including a first electrode connected to a common voltage power line and a gate electrode connected to the first node, wherein the common voltage power line is different from the reset voltage power line, and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another; and a third transistor including a first electrode connected to a second node, a second electrode connected to a signal input line, and a gate electrode connected to a corresponding one of the driving lines, wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor, wherein, during a sensing period within the single frame period, a gate-on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor, and wherein the reset period and the sensing period are not overlapped.
However, in a related field of endeavor, Chang teaches a sensing pixel in figure 3 and further teaches and further teaches a display device comprising an input sensing device (Figure 1, display device 10 and fingerprint sensing layer 120); wherein at least one of the plurality of sensor pixels further comprises: a first transistor including a first electrode connected to a reset voltage power line, a second electrode connected to a first node, and a gate electrode connected to one of the reset control lines (Figure 3, T1 and respective connections); a photodiode including an anode electrode connected to a bias voltage power line and a cathode electrode directly connected to the first node (Figure 3, PD and respective connections), wherein a constant bias voltage is applied to the bias voltage power line ([0040] refers to pulse and thus pulse has constant bias voltage during a period of time); a second transistor including a first electrode connected to a common voltage power line and a gate electrode connected to the first node (Figure 3, T2 and respective connections), wherein the common voltage power line is different from the reset voltage power line (Figures 3-4, SVSS and SVDD), and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another (Figures 3-4, SVSS and SVDD); and a third transistor including a first electrode connected to a second node, a second electrode connected to a signal input line, and a gate electrode connected to a corresponding one of the driving lines (Figure 3, T3 and respective connections), wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor (Figures 3-4, R_SW1), wherein, during a sensing period within the single frame period, a gate- on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor (Figures 3-4, R_SW3), and wherein the reset period and the sensing period are not overlapped ([0032], The transistor T1 may be served as a reset transistor, for resetting the voltage at the node N2 (i.e., reset the electric charges stored in the storage capacitor SC) before the exposure operation. The transistor T2 may be served as a source follower, for forwarding the electronic signal sensed by the optoelectronic element PD and stored in the storage capacitor SC to the sensing line C_SEN after the exposure operation is complete. The transistor T3 may be served as a select transistor, which may be turned on by the corresponding control signal when this pixel is selected (see also figure 6, Reset, exposure and Readout).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a sensing pixel as shown in figures 3-4 with the benefit that the fingerprint sensing pixel, which is configured to realize an optical fingerprint sensor. In addition, three row control signals are sent to the pixel through control signal lines R_SW1-R_SW3, respectively, allowing the pixel to output a sensing signal through a sensing line C_SEN.
Claim(s) 4-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kondo in view of Iwasaki et al. U.S. Patent Publication No. 2011/0181754 (hereafter Iwasaki) and Chang.
Consider claim 4, Kondo teaches an input sensing method comprising: simultaneously applying a reset signal to a plurality of sensor pixels (Figure 8, concurrent reset all pixels); applying a reset voltage in response to the reset signal (Figure 7b, 104) sequentially applying a horizontal driving signal to the plurality of sensor pixels, such that during a sensing period within the single frame period, a gate-on voltage of the horizontal driving signal is applied to a gate electrode of the transistor (Figure 7b-8, Read. Figure 7b, 106); receiving the sensing signal sequentially outputted in response to the horizontal driving signal (Figure 8, read); generating a sensing data signal corresponding to the received sensing signal (Figure 8, read. [0044], MOS imaging device).
Kondo does not appear to specifically disclose correcting the sensing data signal of one of the plurality of sensor pixels, wherein the correcting of the sensing data signal includes dividing the sensing data signal by a value proportional to an amount of time in which the one sensor pixel is exposed to light.
However, in a related field of endeavor, Iwasaki teaches an image pickup device (abstract) and further teaches correcting the sensing data signal of one of the plurality of sensor pixels ([0065], corrects the exposure variation), wherein the correcting of the sensing data signal includes dividing the sensing data signal by a value proportional to an amount of time in which the one sensor pixel is exposed to light ([0078], SIGcorrect=SIGraw*Gi, where Gi=TSh/Treal_i (see also [0077])).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to correct the sensing signal as taught by Iwasaki in order to cope with deterioration of image quality. In addition, high-speed processing is made possible as suggested in [0065] and [0078].
Kondo does not appear to specifically disclose wherein each of the plurality of sensor pixels comprises a first transistor and a second transistor, wherein a gate-on voltage of the reset signal is applied to a gate electrode of the first transistor during a reset period within a single frame period, and wherein a reset voltage power line is electrically connected to a gate electrode of the second transistor via the first transistor; applying a reset voltage to the gate electrode of the second transistor in response to the reset signal, wherein each of the plurality of sensor pixels further comprises a photodiode and a third transistor, wherein the photodiode is directly connected to the gate electrode of the second transistor, and wherein a common voltage power line is electrically connected to the third transistor via the second transistor, wherein the common voltage power line is different from the reset voltage power line, and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another, wherein a constant voltage is applied to an anode electrode of the photodiode; the horizontal driving signal is applied to a gate electrode of the third transistor and wherein the reset period and the sensing period are not overlapped.
However, Chang teaches wherein each of the plurality of sensor pixels comprises a first transistor and a second transistor, wherein a gate-on voltage of the reset signal is applied to a gate electrode of the first transistor during a reset period within a single frame period, and wherein a reset voltage power line is electrically connected to a gate electrode of the second transistor via the first transistor (Figure 3, T1 and T2 and respective connections); applying a reset voltage to the gate electrode of the second transistor in response to the reset signal Figure 3, T1 and T2 and respective connections), wherein each of the plurality of sensor pixels further comprises a photodiode and a third transistor, wherein the photodiode is directly connected to the gate electrode of the second transistor (Figure 3, PD and respective connections), wherein a common voltage power line is electrically connected to the third transistor via the second transistor (Figure 3, T2, T3 and respective connections), wherein the common voltage power line is different from the reset voltage power line (Figures 3-4, SVSS and SVDD), each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another (Figures 3-4, SVSS and SVDD), wherein a constant voltage is applied to an anode electrode of the photodiode ( and figures 3-4 and [0040] refers to pulse and thus pulse has constant bias voltage during a period of time); the horizontal driving signal is applied to a gate electrode of the third transistor (Figure 3, R_SW3) and wherein the reset period and the sensing period are not overlapped ([0032], the transistor T1 may be served as a reset transistor, for resetting the voltage at the node N2 (i.e., reset the electric charges stored in the storage capacitor SC) before the exposure operation. The transistor T2 may be served as a source follower, for forwarding the electronic signal sensed by the optoelectronic element PD and stored in the storage capacitor SC to the sensing line C_SEN after the exposure operation is complete. The transistor T3 may be served as a select transistor, which may be turned on by the corresponding control signal when this pixel is selected (see also figure 6, Reset, exposure and Readout)).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a sensing pixel as shown in figures 3-4 with the benefit that the fingerprint sensing pixel, which is configured to realize an optical fingerprint sensor. In addition, three row control signals are sent to the pixel through control signal lines R_SW1-R_SW3, respectively, allowing the pixel to output a sensing signal through a sensing line C_SEN.
Consider claim 5, Kondo, Iwasaki and Chang teach all the limitations of claim 4. In addition, Iwasaki teaches wherein an amplitude of the sensing signal increases in proportion to a period between a time point the reset signal is applied and a time point the horizontal driving signal is applied (Figure 12, Treal(i+1) is longer than Treal(i-1) and thus larger amplitude. [0073], Tesht indicating the electronic reset timing. [0074-0075], read from the image pickup device (see motivation to combine in claim 4)).
Consider claim 6, Kondo, Iwasaki and Chang teach all the limitations of claim 4. In addition, Kondo teaches wherein the simultaneously applying of the reset signal to the plurality of sensor pixels further comprises providing the reset signal to the plurality of sensor pixels a plurality of times (Figure 9, plurality of times for RS1-RSm) before applying the horizontal driving signal to the plurality of sensor pixels (Figure 9, before SEL1-SELm).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7-9 of U.S. Patent No. 11,837,010 in view of Chang. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Claim 1
Patent
An input sensing device comprising: a plurality of sensor pixels connected to a reset control line
Claim 1: An input sensing device comprising: a plurality of sensor pixels
Claim 8: a reset circuit that is connected to the plurality of sensor pixels and a reset signal control line and simultaneously applies a reset voltage to the plurality of sensor pixels.
wherein each sensor pixel of the plurality of sensor pixels is connected to one of a plurality of driving lines
Claim 1: where each sensor pixel is connected to a corresponding one of a plurality of driving lines
a reset circuit configured to apply a reset signal through reset control lines connected to each of the plurality of sensor pixels
Claim 8: a reset circuit that is connected to the plurality of sensor pixels and a reset signal control line and simultaneously applies a reset voltage to the plurality of sensor pixels.
and a horizontal driver configured to sequentially apply a horizontal driving signal to the sensor pixels through the driving lines
Claim 1: a horizontal driver configured to sequentially apply a horizontal driving signal to the plurality of sensor pixels through the driving lines
wherein the reset circuit simultaneously applies a reset signal to the plurality of sensor pixels.
Claim 8: a reset circuit that is connected to the plurality of sensor pixels and a reset signal control line and simultaneously applies a reset voltage to the plurality of sensor pixels.
wherein at least one of the plurality of sensor pixels further comprises: a first transistor including a first electrode connected to a reset voltage power line, a second electrode connected to a first node, and a gate electrode connected to one of the reset control lines; a photodiode including an anode electrode connected to a bias voltage power line and a cathode electrode directly connected to the first node, wherein a constant bias voltage is applied to the bias voltage power line; a second transistor including a first electrode connected to a common voltage power line and a gate electrode connected to the first node, wherein the common voltage power line is different from the reset voltage power line, and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another; and a third transistor including a first electrode connected to a second node, a second electrode connected to a signal input line, and a gate electrode connected to a corresponding one of the driving lines.
Claim 9: wherein at least one of the plurality of sensor pixels comprises: a first transistor including a first electrode connected to the reset voltage power source, a second electrode connected to a first node, and a gate electrode connected to the reset signal control line; a photodiode including an anode electrode connected to the bias voltage power line and a cathode electrode connected to the first node; a second transistor including a first electrode connected to the common voltage power line, a second electrode connected to a second node, and a gate electrode connected to the first node; and the pixel transistor including a first electrode connected to the second node, a second electrode connected to the signal input line, and a gate electrode connected to the driving line.
wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor, wherein, during a sensing period within the single frame period, a gate- on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor, and wherein the reset period and the sensing period are not overlapped.
As can be seen, besides the wording, Patent includes all the limitations of claim 1 with the exception of wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor, wherein, during a sensing period within the single frame period, a gate- on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor, and wherein the reset period and the sensing period are not overlapped; and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another.
However, Chang teaches wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor (Figures 3-4, R_SW1), wherein, during a sensing period within the single frame period, a gate- on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor (Figures 3-4, R_SW3), and wherein the reset period and the sensing period are not overlapped ([0032]); and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another (Figures 3-4, SVSS and SVDD).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a sensing pixel as shown in figures 3-4 with the benefit that the fingerprint sensing pixel, which is configured to realize an optical fingerprint sensor. In addition, three row control signals are sent to the pixel through control signal lines R_SW1-R_SW3, respectively, allowing the pixel to output a sensing signal through a sensing line C_SEN.
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7-9 of U.S. Patent No. 11,837,010 in view of Chang and further in view of Kondo.
Patent does not appear to specifically disclose the reset circuit applies the reset signal to the plurality of sensor pixels a plurality of times before applying the horizontal driving signal to the sensor pixels.
However, Kondo teaches wherein the reset circuit applies the reset signal to the plurality of sensor pixels a plurality of times (Figure 9, plurality of times for RS1-RSm) before applying the horizontal driving signal to the sensor pixels (Figure 9, before SEL1-SELm).
Therefore, it would have been obvious to provide row reset signals in order to photodiodes of the pixels corresponding to all rows are thereby reset as suggested in [0047].
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 7-9 of U.S. Patent No. 11,837,010 in view of Chang.
Response to Arguments
Applicant's arguments filed 02/19/2026 have been fully considered but they are not persuasive.
On page 8, Applicant argues that “Contrary to Applicant's claims 1, 4 and 7, in Chang, the light-receiving element PD receives a pulse signal at its anode electrode. According to this configuration, the sensing of whether a current flows through the light-receiving element only occurs during a period in which a high-level voltage is applied. Thus, Chang does not disclose that a constant voltage is applied to the anode electrode of the light- receiving element.” The Office respectfully disagrees for the following reason.
Claim recites wherein a constant bias voltage is applied to the bias voltage power line. Thus, “a pulse” meets the claim limitation since a pulse has constant bias voltage during a period of time (see also [0040]). Consequently, these arguments have been considered but they are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621