DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/01/2026 has been entered.
Terminal Disclaimer
The terminal disclaimer filed on 04/30/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 11837010 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosset at al. U.S. Patent Publication No. 2022/0014691 (hereinafter Bosset) in view of Yamahira U.S. Patent Publication No. 2018/0278877 (hereinafter Yamahira).
Consider claim 1, Bosset teaches an input sensing device comprising (Figure 2): a plurality of sensor pixels connected to a reset control line (Figure 2, Phi_ran(i)), wherein each sensor pixel of the plurality of sensor pixels is connected to one of a plurality of driving lines (Figure 2, Phi_ligne(i)); a reset circuit configured to apply a reset signal through the reset control line (Figure 2, Phi_ran(i)); and a horizontal driver configured to sequentially apply a horizontal driving signal to the sensor pixels through the driving lines (Figure 2, [0007] and [0041], Phi_ligne(i)), wherein the reset circuit applies the reset signal to the plurality of sensor pixels [0042], and wherein at least one of the plurality of sensor pixels further comprises: a first transistor including a first electrode connected to a reset voltage power line, a second electrode connected to a first node, and a gate electrode connected to the reset control line (Figure 2, T1 and respective connections); a photodiode including an anode electrode connected to a bias voltage power line and a cathode electrode directly connected to the first node, wherein a constant bias voltage is applied to the bias voltage power line (Figure 2, D and respective connections); a second transistor including a first electrode connected to a common voltage power line and a gate electrode connected to the first node (Figure 2, T2 and respective connections), wherein the common voltage power line is different from the reset voltage power line, and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another (Figure 2, V_ran and Vdd); and a third transistor including a first electrode connected to a second node, a second electrode connected to a signal input line, and a gate electrode connected to a corresponding one of the driving lines (Figure 2, T3 and respective connections), wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor ([0042-0043], reset operation; Figure 2, T1), wherein, during a sensing period within the single frame period, a gate-on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor ([0043], read phase; Figure 2, T3), and wherein the reset period and the sensing period are not overlapped [0043].
Bosset does not appear to specifically disclose a single reset, simultaneously applies the single reset signal to the plurality of sensor pixels.
However, in a related field of endeavor, Yamahira teaches a solid-state image-capturing (abstract) and further teaches a single reset, simultaneously applies the single reset signal to the plurality of sensor pixels (Figure 4b, reset all rows).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to reset simultaneously as taught by Yamahira with the benefit that circuit may perform global reset of simultaneously setting the first node and subsequently global exposure as suggested in [0019].
Consider claim 2, Bosset and Yamahira teach all the limitations of clam 1. In addition, Yamahira teaches wherein the reset circuit applies the single reset signal to the plurality of sensor pixels (Figure 4b, reset all rows) a plurality of times before applying the horizontal driving signal to the sensor pixels (Figure 4a, plurality of RST before t1 and SEL after t8), see motivation to combine in claim 1).
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bosset in view of Yamahira and further in view of Iwasaki et al. U.S. Patent Publication No. 2011/0181754 (hereafter Iwasaki).
Consider claim 4, Bosset teaches an input sensing method comprising: applying a reset signal to a plurality of sensor pixels (Figure 2, Phi_ran(i)), wherein each of the plurality of sensor pixels comprises a first transistor and a second transistor (Figure 2, T1-T2), wherein a gate-on voltage of the reset signal is applied to a gate electrode of the first transistor during a reset period within a single frame period, and wherein a reset voltage power line is electrically connected to a gate electrode of the second transistor via the first transistor; applying a reset voltage to the gate electrode of the second transistor in response to the reset signal (Figure 2, T1-T2, Phi_ran(i) and respective connections), wherein each of the plurality of sensor pixels further comprises a photodiode and a third transistor, wherein the photodiode is directly connected to the gate electrode of the second transistor, wherein a common voltage power line is electrically connected to the third transistor via the second transistor (Figure 2, D, T3 and T2 and respective connections), wherein the common voltage power line is different from the reset voltage power line, wherein each of the common voltage power line and the reset voltage power line extends into a same one of the plurality of sensor pixels separately from one another (Figure 2, V_ran and Vdd), and wherein a constant voltage is applied to an anode electrode of the photodiode (Figure 2, D and respective connections); sequentially applying a horizontal driving signal to the plurality of sensor pixels, such that during a sensing period within the single frame period, a gate-on voltage of the horizontal driving signal is applied to a gate electrode of the third transistor (Figure 2, [0007] and [0041], Phi_ligne(i)); receiving the sensing signal sequentially outputted in response to the horizontal driving signal (Figure 2, [0007] and [0041], Phi_ligne(i)); generating a sensing data signal corresponding to the received sensing signal (Figure 2, [0007] and [0041], Phi_ligne(i)); and wherein the reset period and the sensing period are not overlapped [0043].
Bosset does not appear to specifically disclose simultaneously applying a single reset signal to a plurality of sensor pixels.
However, Yamahira teaches simultaneously applying a single reset signal to a plurality of sensor pixels (Figure 4b, reset all rows).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to reset simultaneously as taught by Yamahira with the benefit that circuit may perform global reset of simultaneously setting the first node and subsequently global exposure as suggested in [0019].
Bosset does not appear to specifically disclose correcting the sensing data signal of one of the plurality of sensor pixels, wherein the correcting of the sensing data signal includes dividing the sensing data signal by a value proportional to an amount of time in which the one sensor pixel is exposed to light.
However, in a related field of endeavor, Iwasaki teaches an image pickup device (abstract) and further teaches correcting the sensing data signal of one of the plurality of sensor pixels ([0065], corrects the exposure variation), wherein the correcting of the sensing data signal includes dividing the sensing data signal by a value proportional to an amount of time in which the one sensor pixel is exposed to light ([0078], SIGcorrect=SIGraw*Gi, where Gi=TSh/Treal_i (see also [0077])).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to correct the sensing signal as taught by Iwasaki in order to cope with deterioration of image quality. In addition, high-speed processing is made possible as suggested in [0065] and [0078].
Consider claim 5, Bosset, Yamahira and Iwasaki teach all the limitations of claim 4. In addition, Iwasaki teaches wherein an amplitude of the sensing signal increases in proportion to a period between a time point the reset signal is applied and a time point the horizontal driving signal is applied (Figure 12, Treal(i+1) is longer than Treal(i-1) and thus larger amplitude. [0073], Tesht indicating the electronic reset timing. [0074-0075], read from the image pickup device (see motivation to combine in claim 4)).
Consider claim 6, Bosset, Yamahira and Iwasaki teach all the limitations of claim 4. In addition, Yamahira teaches wherein the simultaneously applying of the reset signal to the plurality of sensor pixels (Figure 4b, reset all rows) further comprises providing the reset signal to the plurality of sensor pixels a plurality of times before applying the horizontal driving signal to the plurality of sensor pixels (Figure 4a, plurality of RST before t1 and SEL after t8), see motivation to combine in claim 1).
Consider claim 7, Bosset teaches an input sensing device comprising: a plurality of sensor pixels connected to a reset control line (Figure 2, Phi_ran(i)), wherein each sensor pixel of the plurality of sensor pixels is connected to one of a plurality of driving lines (Figure 2, Phi_ligne(i)); a reset circuit configured to apply a reset signal through the reset control line (Figure 2, Phi_ran(i)); and a horizontal driver configured to sequentially apply a horizontal driving signal to the sensor pixels through the driving lines (Figure 2, [0007] and [0041], Phi_ligne(i)), and wherein at least one of the plurality of sensor pixels further comprises: a first transistor including a first electrode connected to a reset voltage power line, a second electrode connected to a first node, and a gate electrode connected to the reset control line (Figure 2, T1 and respective connections); a photodiode including an anode electrode connected to a bias voltage power line and a cathode electrode directly connected to the first node, wherein a constant bias voltage is applied to the bias voltage power line (Figure 2, D and respective connections); a second transistor including a first electrode connected to a common voltage power line and a gate electrode connected to the first node (Figure 2, T2 and respective connections), wherein the common voltage power line is different from the reset voltage power line, and each of the common voltage power line and the reset voltage power line extends into the at least one of the plurality of sensor pixels separately from one another (Figure 2, V_ran and Vdd); and a third transistor including a first electrode connected to a second node, a second electrode connected to a signal input line, and a gate electrode connected to a corresponding one of the driving lines (Figure 2, T3 and respective connections), wherein, during a reset period within a single frame period, a gate-on voltage of the reset signal is applied to the gate electrode of the first transistor ([0042-0043], reset operation; Figure 2, T1), wherein, during a sensing period within the single frame period, a gate-on voltage of the horizontal driving signal is applied to the gate electrode of the third transistor ([0043], read phase; Figure 2, T3), and wherein the reset period and the sensing period are not overlapped [0043].
Bosset does not appear to specifically disclose single reset control line, wherein the reset circuit simultaneously applies the single reset signal to the plurality of sensor pixels.
However, Yamahira teaches single reset control line, wherein the reset circuit simultaneously applies the single reset signal to the plurality of sensor pixels (Figure 4b, reset all rows).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to reset simultaneously as taught by Yamahira with the benefit that circuit may perform global reset of simultaneously setting the first node and subsequently global exposure as suggested in [0019].
Bosset does not appear to specifically disclose a display device comprising: an input sensing device.
However, Iwasaki teaches a display device comprising: an input sensing device ([0030], display section).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a display device as taught by Iwasaki the display section is intended to display the image photographed and processed for display as suggested in [0037].
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621
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