DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-6 and 8-15 in the reply filed on 5/01/26 is acknowledged.
Claims 7 and 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/01/26.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 11/09/23. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US PGPub 2021/0035935, hereinafter referred to as “Chen”).
Chen discloses the semiconductor device as claimed. See figures 1A-19 and corresponding text, where Chen teaches, in claim 1, a bonding structure including a component and a bonding surface, the bonding structure comprising:
the bonding surface including a first bonding region (152), a second bonding region (150) and at least one bonding wiring, wherein the first bonding region includes a plurality of first bonding pads (120) and a first bonding insulation layer (106), the first bonding pads (120) have a first density distributed in the first bonding region (152), and the first bonding insulation layer (106) is positioned between the first bonding pads (120), wherein the second bonding region (150) includes a plurality of second bonding pads (110) and a second bonding insulation layer (106), the second bonding pads (110) have a second density lower than the first density and are distributed in the second bonding region (150), and the second bonding insulation layer (106) is positioned between the second bonding pads (110), and wherein the at least one bonding wiring is arranged at the second bonding region (150), and the at least one bonding wiring is configured to receive and transfer an external voltage to the component (figures 1-3; [0030-0038]).
Chen teaches, in claim 2, further comprising a plurality of interconnections configured to electrically connect the first bonding pads, the second bonding pads and the bonding wiring with conductive terminals of the component (figures 1-3; [0030-0038]).
Chen teaches, in claim 3, wherein the bonding wiring is arranged in the second bonding region to maintain a percentage of the second bonding insulation layer to a unit area of the second bonding region within a prescribed range (figures 1-3; [0030-0038]).
Chen teaches, in claim 4, wherein the percentage of the first bonding insulation layer to the unit area of the first bonding region is maintained within the prescribed range (figures 1-3; [0030-0038]).
Chen teaches, in claim 5, wherein the prescribed range is an occupying area of the first bonding insulation layer or the second bonding insulation layer by the unit area and the prescribed range is from 50% to about 90% of the unit area (figures 1-3; [0030-0038]).
Chen teaches, in claim 6, wherein the external voltage provided to the bonding wiring comprises at least one or more of a power, an operation signal and an address provided to the component (figures 1-3; [0030-0038]).
Chen teaches, in claim 8, a stack type semiconductor device comprising:
a first structure (400) including a first bonding region (450) and a second bonding region (452), the first bonding region including a plurality of first bonding pads (410) and a first bonding insulation layer positioned between the first bonding pads (410), and the second bonding region (452) including at least one second bonding pad, a second bonding insulation layer configured to insulate the second bonding pad, and at least one first bonding wiring positioned in the second bonding insulation layer (figure 7A; [0052-0056]); and
a second structure (500) including a third bonding region and a fourth bonding region, the third bonding region including a plurality of third bonding pads (510) hybrid-bonded to the first bonding pads (410), and a third bonding insulation layer hybrid-bonded to the first bonding insulation layer, wherein the fourth bonding region includes a fourth bonding pad (510) hybrid-bonded to the second bonding pad, a fourth bonding insulation layer hybrid-bonded to at least one of the second bonding insulation layer and the first bonding wiring, and wherein at least one second bonding wiring is hybrid-bonded to at least one of the at least one first bonding wiring and the second bonding insulation layer (figures 7A-9; [0052-0061]).
Chen teaches, in claim 9, wherein an area ratio between the first bonding insulation layer and the third bonding insulation layer and an area ratio between the second bonding insulation layer and the fourth bonding insulation layer are within a prescribed range (figures 7A-9; [0052-0061]).
Chen teaches, in claim 10, wherein the prescribed range comprises a bonding occupying ratio between the first bonding insulation layer and the third bonding insulation layer or between the second bonding insulation layer and the fourth bonding insulation layer, and the bonding occupying ratio is based on a unit area on a bonding surface between the first structure and the second structure, and the prescribed range is from 50% to about 90% of the unit area (figures 7A-9; [0052-0061]).
Chen teaches, in claim 11, further comprising:
a first component including a plurality of conductive terminals electrically connected with the first structure; and a second component including a plurality of conductive terminals electrically connected with the second structure (figures 7A-9; [0052-0061]).
Chen teaches, in claim 12, wherein the first structure comprises a plurality of first interconnections configured to connect the first bonding pads, the second bonding pads and the first bonding wiring with the conductive terminals of the first component (figures 7A-9; [0052-0061]).
Chen teaches, in claim 13, wherein the at least one first bonding wiring receives a voltage corresponding to a power, and at least one of an operation signal and the voltage is transmitted to the conductive terminals of the first component through the first interconnections (figures 7A-9; [0052-0061]).
Chen teaches, in claim 14, wherein the second structure comprises a plurality of second interconnections configured to connect the third bonding pads, the fourth bonding pads and the second bonding wiring with the conductive terminals of the second component (figures 7A-9; [0052-0061]).
Chen teaches, in claim 15, wherein the second bonding wiring receives at least one of a voltage corresponding to a power, an operation signal, and an address, and the voltage is transmitted to the conductive terminals of the second component through the second interconnections (figures 7A-9; [0052-0061]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 May 30, 2026
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