DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-6, 8, 9, 11-16, 18, and 20-24 in the reply filed on 3/05/26 is acknowledged.
Claims 7, 10, 17, and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/05/26.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 11/09/23. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 1, lines 5 and 15, respectively, it is unclear if the “a first cell-periphery structure” is in the “cell region” or is “the first cell-periphery structure in the peripheral region”.
In claim 12, lines 12 and 18 respectively, it is unclear if the “a first cell-periphery structure” is in the “cell region” or is “the first cell-periphery structure in the peripheral region”.
In claim 21, in line 4, it is unclear if the “a first conductive layer” is included in the patterning of the first region. In addition, it is unclear where is the “first conductive layer” since the forming of “a second conductive line structure by patterning the first and second structures in the second region, when the first structure is only in the first region.
For purpose of examination on the merits the examiner will view only the cell region the first cell-periphery structure and the second cell-periphery structure in the peripheral region. In addition, regarding claim 21 the examiner will view the first and second conductive layers to be in first and second regions separately.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 8, 9, 11, 12, 18, and 20-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin (US PGPub 2012/0153363, hereinafter referred to as “Shin”), IDS reference).
Shin discloses the semiconductor method as claimed. See figures 1-3E and corresponding text, where Shin teaches, in claim 1, a method of manufacturing a semiconductor device, the method comprising:
providing a substrate (51) having a cell region and a peripheral region (figure 2; [0019-0026]);
forming a first cell-periphery structure (56) including a conductive layer over a surface of the substrate (51); (figure 3D; [0040-0043])
forming a cell bit line trench (70) by patterning the first cell-periphery structure in the cell region; (figure 3D; [0040-0043])
forming a second cell-periphery structure (74) including a second conductive layer over the surface of the substrate (53), wherein the second cell-periphery structure forms a cell bit line structure filling the cell bit line trench (74) in the cell region, and wherein the second cell-periphery structure including the second conductive layer is disposed over the first cell-periphery structure in the cell region (figure 3E; [0045-0048]); and
forming a periphery gate structure (62) by patterning the first and second cell-periphery structures in the peripheral region (figures 3B,3D and 3E; [0032-0047]).
Shin teaches, in claim 2, wherein forming the first cell-periphery structure includes: (figures 3B and 3C; [0032-0039])
forming a dielectric layer (64, 65) over the substrate in the cell region and the peripheral region; and
forming the first conductive layer (70) over the dielectric layer.
Shin teaches, in claim 4, wherein the first cell-periphery structure further includes a periphery gate dielectric layer (59) formed between the substrate and the first conductive layer in the peripheral region (figures 3B-3E; [0032]).
Shin teaches, in claim 8, further comprising performing a planarization process over the second cell-periphery structure after forming the second cell-periphery structure, wherein in the planarization process, the second cell-periphery structure formed outside the cell bit line trench is removed to expose the first cell-periphery structure in the cell region (figures 3A-3E; [0028-0047]).
Shin teaches, in claim 9, further comprising removing the first cell-periphery structure in the cell region after forming the second cell-periphery structure (figures 3A-3E; [0028-0047]).
Shin teaches, in claim 11, further comprising:
forming a cell gate structure (56) buried in the substrate (53) in the cell region; and
forming a cell contact plug (67) and an interlayer insulation layer (64, 65) surrounding the cell contact plug (67) over the substrate (53) in the cell region, wherein the cell contact plug (67) electrically connects the substrate (53) and the cell bit line (70) structure to each other (figures 3A-3E; [0028-0047]).
Shin teaches, in claim 12, a method of manufacturing a semiconductor device, the method comprising: (figures 3A-3E; [0028-0047])
providing a substrate (53) having a cell region and a peripheral region;
forming a cell gate structure buried (56) in the substrate (53) in the cell region;
forming a cell contact plug (67) and an interlayer insulation layer (64, 65) surrounding the cell contact plug (67) over the substrate (53) in the cell region;
forming a first cell-periphery structure (70) including a first conductive layer over a surface of the substrate (53);
forming a cell bit line trench (70) exposing the cell contact plug (67) by patterning the first cell-periphery structure in the cell region;
forming a second cell-periphery structure (74) including a second conductive layer over the surface of the substrate (53), wherein the second cell-periphery structure forms a cell bit line structure wherein the second cell-periphery structure (74) including the second conductive layer is disposed over the first cell-periphery structure in the peripheral region; and
forming a periphery gate structure (62) by patterning the second cell-periphery structures in the peripheral region.
Shin teaches, in claim 13, wherein forming the first cell-periphery structure includes: (figures 3A-3E; [0028-0047])
forming a dielectric layer over the substrate in the cell region and the peripheral region; and
forming the first conductive layer over the dielectric layer.
Shin teaches, in claim 18, further comprising performing a planarization process over the second cell-periphery structure after forming the second cell-periphery structure, wherein in the planarization process, the second cell-periphery structure formed outside the cell bit line trench is removed to expose the first cell-periphery structure in the cell region (figures 3A-3E; [0028-0047]).
Shin teaches, in claim 20, further comprising forming an interlayer insulation layer over the entire surface of the substrate after removing the first cell-periphery structure in the cell region, wherein forming the periphery gate structure further includes patterning the interlayer insulation layer (figures 3A-3E; [0028-0047]).
Shin teaches, in claim 21, a method of manufacturing a semiconductor device, the method comprising: (figures 3A-3E; [0028-0047])
providing a substrate (53) having a first region and a second region;
forming a first structure (70) including a first conductive layer over a surface of the substrate (53);
forming a trench by patterning the first structure (70) in the first region;
forming a second structure (74) including a second conductive layer over the surface of the substrate (53), wherein the second structure forms a first conductive line structure wherein the second structure (74) including the second conductive layer disposed over the second region.
Shin teaches, in claim 22, wherein the first region includes a cell region, and the second region includes a peripheral region (figures 3A-3E; [0028-0047]).
Shin teaches, in claim 23, wherein forming the first conductive line structure includes forming a cell bit line structure in the cell region (figures 3A-3E; [0028-0047]).
Shin teaches, in claim 24, wherein forming the second conductive line structure includes forming a periphery gate structure in the peripheral region (figures 3A-3E; [0028-0047]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 5, 6, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US PGPub 2012/0153363, hereinafter referred to as “Shin”), IDS reference as applied to claims 1 and 12 above, and further in view of Park et al. (US PGPub 2011/0133283, hereinafter referred to as “Park”).
Shin discloses the semiconductor method substantially as claimed. See the rejection above.
In addition, Shin shows, in claim 3, [0035], teaches conventional technologies.
However, Shin fails to explicitly show, in claim 3, wherein the dielectric layer includes at least one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and hafnium zirconium oxide; wherein the first conductive layer includes polysilicon.
Park teaches, in claim 3, a similar device that includes forming the an interlayer formed of, BoroPhosphoSilicate Glass (BPSG), Spin On Dielectric (SOD) or High Density Plasma (HDP) material insulating layer and polysilicon bit line ([0054], [0059-0060]). In addition, Park provides the advantages of reducing parasitic capacitance [0006],([0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the dielectric layer includes at least one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and hafnium zirconium oxide; wherein the first conductive layer includes polysilicon, in the method of Shin, according to the teachings of Park, with the motivation of reducing parasitic capacitance.
Shin fails to explicitly show, in claim 5, wherein forming the cell bit line structure includes: forming a barrier layer along an inner surface of the cell bit line trench in the cell region; and
filling the cell bit line trench in which the barrier layer is formed with the second conductive layer.
Park teaches, in claim 5, a similar device that includes forming a barrier layer within to construct a bit line contact plug ([0060],[0066]). In addition, Park provides the advantages of reducing parasitic capacitance [0006],([0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein forming the cell bit line structure includes: forming a barrier layer along an inner surface of the cell bit line trench in the cell region; and
filling the cell bit line trench in which the barrier layer is formed with the second conductive layer, in the method of Shin, according to the teachings of Park, with the motivation of reducing parasitic capacitance.
Shin in view of Park show, in claim 6, wherein the barrier layer includes at least one or more of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), and tungsten silicon nitride (WSiN), and wherein the second conductive layer includes tungsten (W) ([0060], Park).
Shin iteaches, in claim 14, wherein the dielectric layer includes at least one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and hafnium zirconium oxide, and wherein the first conductive layer includes polysilicon.
Park teaches, in claim 14, a similar device that includes forming the an interlayer formed of, BoroPhosphoSilicate Glass (BPSG), Spin On Dielectric (SOD) or High Density Plasma (HDP) material insulating layer and polysilicon bit line ([0054], [0059-0060]). In addition, Park provides the advantages of reducing parasitic capacitance [0006],([0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the dielectric layer includes at least one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, and hafnium zirconium oxide, and wherein the first conductive layer includes polysilicon, in the method of Shin, according to the teachings of Park, with the motivation of reducing parasitic capacitance.
Shin fails to explicitly show, in claim 15, wherein forming the cell bit line structure includes:
forming a barrier layer along an inner surface of the cell bit line trench in the cell region; and
filling the cell bit line trench in which the barrier layer is formed with the second conductive layer.
Park teaches, in claim 15, a similar device that includes forming a barrier layer within to construct a bit line contact plug ([0060],[0066]). In addition, Park provides the advantages of reducing parasitic capacitance [0006],([0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein forming the cell bit line structure includes:
forming a barrier layer along an inner surface of the cell bit line trench in the cell region; and
filling the cell bit line trench in which the barrier layer is formed with the second conductive layer, in the method of Shin, according to the teachings of Park, with the motivation of reducing parasitic capacitance.
Shin in view of Park shows, in claim 16, wherein the barrier layer includes at least one or more of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), and tungsten silicon nitride (WSiN), and wherein the second conductive layer includes tungsten (W) [0060], Park).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 April 4, 2026