DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 07/30/2026 has been entered. Claims 1-20 remain pending in the application. Applicant’s amendments have overcome every claim objection and every 112(b) rejections previously set forth in the Non-Final Office Action mailed on 03/02/2026.
Specification
The corrections made to the specification and received on 07/30/2026 are acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/22/2026 has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11, 12, 16 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation “bonding the conductive pads”. There is insufficient antecedent basis for this limitation. For the purpose of examination, claim 11 will be interpreted as: The method as claimed in claim 1, further comprising providing a wafer having a non-conductive dielectric layer surrounding conductive contacts of the wafer, and bonding the conductive bumps
Claims 12, 16, and 18 recite the limitation “die assembly that is similar to the reconstituted die assembly”. The term “similar” is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. This language is indefinite as the specification does not describe what is required of die assembly to be considered “similar” to the reconstituted die assembly. Similar may refer to structure, dimensions, number of conductive bumps or dies, or other characteristics of a die assembly. For the purpose of examination “similar” will be interpreted as having the same size in a horizontal direction of a cross sectional view.
Claims 17-20 are also rejected as being dependent on claim 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-6, 8-10, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over disclosed prior art, Wu et al., (United States Patent Application Publication Number, US 2020/0194393 A1), hereinafter referenced as Wu, in view of Chen et al., (United States Patent Application Publication Number, US 2022/0223553 A1) hereinafter referenced as Chen, and in view of Yu et al., (United States Patent Application Publication Number, US 2019/0109118 A1) hereinafter referenced as Yu.
Regarding claim 1, Wu teaches a method of manufacturing an integrated device package, comprising the steps of: preparation of a plurality of dies (Fig.5, elements #50A and #50B) for bonding by forming a layer on a first side of each of the plurality of dies (Fig.5, layer, element #118 is formed on the bottom side of the dies, element #50A and #50B in region 100A). Wu teaches the layer is an adhesive (paragraph [0032], rows 1-2). Although adhesives can form non-conductive dielectric layers, Wu does not explicitly teach the adhesive is a non-conductive dielectric layer. Chen teaches forming a non-conductive dielectric layer on a fist side of each if the plurality of dies (Fig.2, non-conductive dielectric layer, element #F1, paragraph [0024], rows 3-6, is formed on the bottom side of dies, elements #100). Thus, both references Wu and Chen teach forming a layer of a first side of dies, that is used to bond the dies to a carrier. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the adhesive disclosed by Wu could have been replaced for the silicon oxide layer disclosed by Chen because both serve the same purpose of providing a layer used to attach the dies to a carrier. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a layer used to attach the dies to a carrier. The silicon oxide layer disclosed by Chen is bonded by fusion bonding to the non-conductive dielectric layer on the first side of the carrier (paragraph [0027], rows 1-5), which allows for a more robust connection as compared to the adhesive disclosed by Wu. Note that both references disclose the non-conductive dielectric layer on the first side of the carrier as silicon oxide (Wu, element #112, paragraph [0028], rows 6-8, and Chen, element Fc1, paragraph [0025], rows 12-14).
Wu further teaches forming a plurality of die connectors, conductive pillars, on a second side of each die opposite to the first side (Fig.1, elements #66, paragraph [0017], rows 8-10 are formed on the top side of each die before bonding. Note the element #68 may not be present on the top side of the dies, paragraph [0019], rows 1-2). The combination of Wu and Chen does not teach forming a plurality of conductive bumps. Yu teaches forming a plurality of conductive bumps on a second side of each die opposite to the first side (Fig.2, element #126, paragraph [0010], rows 1-2). Thus, both references Wu and Yu teach electrical connections formed on a side of each die. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the die connectors disclosed by Wu could have been replaced for the bumps disclosed by Yu, because both serve the same purpose of providing electrical connections for dies. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection for connecting the dies to circuit boards or power sources. Conductive bumps have low inductance and can be arranged across an entire die surface, enabling high contact densities, and making them suitable for high-speed digital circuits connections.
Wu further teaches preparation of a carrier by forming a first non-conductive dielectric layer on a first side of the carrier (Fig.5, element #112, paragraph [0031], rows 1-2); bonding the plurality of dies sequentially to the carrier by adhering the first non-conductive dielectric layer on the first side of each die to the first non-conductive dielectric layer on the first side of the carrier (paragraph [0031], rows 1-2); forming a filling non-conductive dielectric layer on the carrier and the plurality of dies bonded onto the carrier until the plurality of dies is covered by the filling non-conductive dielectric layer (Fig.6, element #142, the encapsulant is non-conductive otherwise will short vias #116 and the invention will not work); removing a portion of the filling non-conductive dielectric layer to planarize and expose conductive bumps located on the second side of the plurality of dies (Fig.7, paragraph [0034], rows 1-6) to form a reconstituted die assembly (Fig.7, each region #100A and #100B, forms a reconstituted die assembly), in which the plurality of dies are arranged as a single assembly (Fig.7, the plurality of dies in region #100A form a single assembly), configured to collectively electrically connect the conductive bumps of the plurality of dies to an external electronic device (As noted above Yu teaches bumps, and Wu in Fig.7, the conductive bumps are exposed and therefore are configured to be connect to external electronic device).
Regarding claim 2, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. Wu further teaches the method as claimed in claim 1, wherein the preparation of the plurality of dies further comprises the steps of: forming the first non-conductive dielectric layer on a first side of a wafer which contains the plurality of dies; and singulating the wafer to separate the plurality of dies (paragraph [0032], rows 8-11).
Regarding claim 4, the combination of Wu, Chen and Yu teaches the method of claims 1 and 2 as set forth in the obviousness rejection. Wu further teaches the method as claimed in claim 2, further comprising the step of selecting only known good dies from the plurality of dies that have been separated to be bonded onto the carrier (paragraph [0045], rows 10-13).
Regarding claim 5, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. Wu teaches the method as claimed in claim 1, wherein the first non-conductive dielectric layer on the first side of the carrier consists only of an inorganic dielectric material (paragraph [0028], rows 6-8). Wu teaches wherein the first layer on the first sides of the plurality of dies consists of an adhesive (element #118, paragraph [0031], rows 1-2). Wu does not teach wherein the first non-conductive dielectric layer on the first sides of the plurality of dies consist only of an inorganic dielectric material. Chen teaches wherein the first non-conductive dielectric layer on the first sides of the plurality of dies consist only of an inorganic dielectric material (Fig.2, non-conductive dielectric layer, element #F1, consists of silicon oxide, paragraph [0025], rows 12-14). Thus, both references Wu and Chen teach forming a layer that is used to attach the plurality of dies to a carrier. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the adhesive disclosed by Wu could have been replaced for the silicon oxide layer disclosed by Chen because both serve the same purpose of providing a layer used to attach the plurality of dies to a carrier. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing a layer used to attach the dies to a carrier. The silicon oxide layer disclosed by Chen is bonded by fusion bonding to the non-conductive dielectric layer on the first side of the carrier (paragraph [0027], rows 1-5), which allows for a more robust connection as compared to the adhesive disclosed by Wu. Note that both references disclose the non-conductive dielectric layer on the first side of the carrier as silicon oxide (Wu, element #112, paragraph [0028], rows 6-8, and Chen, element Fc1, paragraph [0025], rows 12-14).
Regarding claim 6, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. Wu teaches the method as claimed in claim 1, wherein the preparation of the plurality of dies further comprises the steps of: forming the first non-conductive dielectric layer on first side of a wafer and singulating the multiple wafers to separate the plurality of dies for bonding (paragraph [0032], rows 8-11). Wu does not teach multiple wafers having different size or types containing the plurality of dies, wherein the plurality of dies consists of dies of different size or types. Yu teaches multiple wafers having different size or types containing the plurality of dies, wherein the plurality of dies consists of dies of different size or types singulated from wafers and prepared for bonding (paragraph [0013], rows 9-15, Fig.3 dies are singulated from wafers). Making dies of different sizes on wafers of different materials is well known in the art, and therefore a prima facie case of obviousness exists (MPEP 2144.03). Therefore, it would have been obvious to prepare multiple wafers of different size or types, containing the plurality of dies, wherein the plurality of dies consists of dies of different size, using the same process as applied to a single wafer, because the results would have been predictable. This allows a repetition of the same process steps and using same fabrication tools, which reduces costs.
Regarding claim 8, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. The combination of Wu and Chen does not teach the method as claimed in claim 1, wherein the preparation of the carrier further comprises the step of fabricating alignment marks on the first side of the carrier for alignment purposes during bonding of the plurality of dies onto the carrier. Yu teaches wherein the preparation of the carrier further comprises the step of fabricating alignment marks on the first side of the carrier for alignment purposes during bonding of the plurality of dies onto the carrier (paragraph [0013], rows 8-10). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Yu and disclose wherein the preparation of the carrier further comprises the step of fabricating alignment marks on the first side of the carrier for alignment purposes during bonding of the plurality of dies onto the carrier. As disclosed by Yu, the dies may be subject to further photomask steps used to connect the contact pads located on the top side of the dies (Fig.8 and 9) and therefore, accurately placing the dies on the carrier using the alignment marks avoids misalignment with the lithography equipment, which can produce defects and therefore decrease yield.
Regarding claim 9, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. Wu does not teach the method as claimed in claim 1, wherein the first non-conductive dielectric layer on first sides of the plurality of dies is adhered to the first non-conductive dielectric layer on the first side of the carrier by annealing the respective non-conductive dielectric layers to each other to solidify their dielectric-to-dielectric bonding and to fix their relative positions. Chen teaches the method as claimed in claim 1, wherein the first non-conductive dielectric layer on first sides of the plurality of dies is adhered to the first non-conductive dielectric layer on the first side of the carrier by annealing the respective non-conductive dielectric layers to each other to solidify their dielectric-to-dielectric bonding and to fix their relative positions (paragraph [0027], rows 1-16). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Chen and disclose wherein the first non-conductive dielectric layer on the first sides of the plurality of dies is adhered to the first non-conductive dielectric layer on the first side of the carrier by annealing the respective non-conductive dielectric layers to each other to solidify their dielectric-to-dielectric bonding and to fix their relative positions. The fusion bonding method disclosed by Chen allows for a more robust connection as compared to using the adhesive disclosed by Wu.
Regarding claim 10, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. Wu further teaches the method as claimed in claim 1, wherein the filling non-conductive dielectric layer is planarized such that top surfaces of the conductive contact bumps and the filling non-conductive dielectric layer are flush with one another (Fig.7, paragraph [0034], rows 6-8).
Regarding claim 13, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. Wu does not teach the method as claimed in claim 1, further comprising providing a second plurality of separated dies having a non-conductive dielectric layer surrounding conductive bumps of each of the second plurality of separated dies, and bonding the second plurality of separated dies to electrically connect the conductive bumps of the second plurality of separated dies to the conductive bumps of the reconstituted die assembly, such combination of the reconstituted die assembly and the second plurality of separated dies forming the integrated device package. Chen teaches the method as claimed in claim 1, further comprising providing a second plurality of separated dies (Fig.17, elements #200) having a non-conductive dielectric layer surrounding conductive contact bumps of each of the second plurality of separated dies (Fig.17, element #BF2, paragraph [0042], rows 1-5), and bonding the second plurality of separated dies to electrically connect the contact bumps of the second plurality of separated dies to the conductive contact pads of the reconstituted die assembly (Fig.17, conductive pads of the second plurality of dies, element #200 are bonded to the conductive pads of the reconstituted die assembly), such combination of the reconstituted die assembly and the second plurality of separated dies forming the integrated device package (Fig.20, they form a device package). Chen does not teach the contact pads are conductive bumps. However, as noted in the obviousness rejection of claim 1, Yu teaches dies having a non-conductive dielectric layer surrounding conductive bumps. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Chen and Yu and disclose providing a second plurality of separated dies having a non-conductive dielectric layer surrounding conductive bumps of each of the second plurality of separated dies, and bonding the second plurality of separated dies to electrically connect the conductive bumps of the second plurality of separated dies to the conductive bumps of the reconstituted die assembly, such combination of the reconstituted die assembly and the second plurality of separated dies forming the integrated device package. This enables integration of multiple dies in the same integrated device package while providing a smaller footprint for the package as compared to having the dies disposed laterally, adjacent to one another and on the same wafer.
Regarding claim 14, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. Wu further teaches the method as claimed in claim 1, further comprising forming one or more redistribution layers onto the planarized filling non-conductive dielectric layer (Fig.12, layers #124, #126, #128, #130, #132, #134, #136, #138 and #140 for redistribution layers on top of element #142) for electrically coupling the conductive bumps (see rejection of claim 1, the conductive pillars disclosed by Wu can be replaced by the conductive bumps disclosed by Yu) to electrical contacts formed on an opposite side of the one or more redistribution layers from the conductive bumps (Fig.21, contacts, elements #246, are formed on the top side of the redistribution layer, which is opposite side from the contact pads and are electrically connected to the pads), such combination of the reconstituted die assembly, the one or more redistribution layers and the electrical contacts forming the integrated device package (Fig.21 shows a package).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chen, Yu and in view of Gao et al., (United States Patent Application Publication Number, US 2025/0096191 A1) hereinafter referenced as Gao.
Regarding claim 3, the combination of Wu, Chen and Yu teaches the method of claims 1 and 2 as set forth in the obviousness rejection. The combination of Wu and Yu further teaches the method as claimed in claim 2, further comprising the step of forming the conductive bumps on a second side of the wafer opposite to the first side (see rejection of claim 1, the conductive pillars disclosed by Wu can be replaced by the conductive bumps disclosed by Yu Fig.2, elements #126 formed on the top side of the wafer).
The combination of Wu, Chen and Yu does not teach grinding the first side of the wafer to thin the wafer prior to forming the first non-conductive dielectric layer on the first side of the wafer. Gao teaches grinding the first side of the wafer to thin the wafer prior to forming the first non-conductive dielectric layer on the first side of the wafer (Fig.4A, 4B, 4C, wafer element #402 is grinded before the non-conductive dielectric layer, element #418 is formed). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Gao and disclose grinding the first side of the wafer to thin the wafer prior to forming the first non-conductive dielectric layer on the first side of the wafer. Thinning the entire wafer increases efficiency versus thinning each die separately and thinning the wafer (and so the dies) reduces brittleness making it more flexible during bonding process.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chen and in view of Oliver et al., (United States Patent Application Publication Number, US 2018/0012932 A1) hereinafter referenced as Oliver.
Regarding claim 7, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. Wu teaches the method as claimed in claim 1, wherein the first non-conductive dielectric layer on the first side the carrier is deposited by chemical vapor deposition (paragraph [0028], rows 6-10). Furthermore, Wu teaches wherein the first non-conductive dielectric layer on the first side the carrier is made of silicon oxide (paragraph [0028], rows 6-8). Chen teaches wherein the first non-conductive dielectric layers on the first sides of the plurality of dies, and the carrier are made of silicon oxide (paragraph [0026], rows 12-14). The combination of Wu and Chen does not teach the method as claimed in claim 1, wherein the first non-conductive dielectric layers on the first sides of the plurality of dies are deposited by plasma-enhanced chemical vapor deposition. Oliver teaches silicon oxide layers deposited by plasma enhanced chemical vapor deposition (paragraph [0077], rows 13-14). Therefore, the combination of Wu, Chen, Yu and Oliver teaches the method as claimed in claim 1, wherein the first non-conductive dielectric layers on the first sides of the plurality of dies and the carrier are deposited by plasma-enhanced chemical vapor deposition. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Oliver and disclose non-conductive dielectric layers deposited by plasma-enhanced chemical vapor deposition. PECVD allows deposition of dielectric materials at lower temperatures as compared to other CVD processes and, considering that the non-conductive dielectric layers are deposited on first sides of the plurality of dies, using low temperature prevents damaging the dies.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chen, Yu and in view of Karhade et al., (United States Patent Application Publication Number, US 2025/0112168 A1) hereinafter referenced as Karhade.
Regarding claim 11, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. The combination of Wu, Chen and Yu does not teach the method as claimed in claim 1, further comprising providing a wafer having a non-conductive dielectric layer surrounding conductive contacts of the wafer, and bonding the conductivebumps of the reconstituted die assembly to the conductive contacts, such combination of the reconstituted die assembly and the wafer forming the integrated device package. Karhade teaches providing a wafer having a non-conductive dielectric layer surrounding conductive contacts of the wafer (Fig.1H, wafer, element #192, has a non-conductive dielectric layer, element #101, surrounding contacts, #195), and bonding the conductive contacts of the reconstituted die assembly to the conductive contacts of the wafer (Fig.1H, elements #195 are connected to elements #140 of the assembly showed in Fig.1G), such combination of the reconstituted die assembly and the wafer forming the integrated device package (Fig.1J, together they form a package). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Karhade and disclose providing a wafer having a non-conductive dielectric layer surrounding conductive contacts of the wafer, and bonding the conductive contacts of the reconstituted die assembly to the conductive contacts of the wafer, such combination of the reconstituted die assembly and the wafer forming the integrated device package. As disclosed by Karhade, the wafer can provide electrical connections between the dies of the reconstituted die assembly (Fig.1H, element #103 and #105), and connections to a package substrate (Fig.1J, substrate #113) which results in increased design flexibility for providing power or transmitting signals to and from the dies of the assembly.
Karhade does not teach the conductive contacts of the reconstituted die assembly are bumps. Yu teaches Yu teaches the conductive contacts of the reconstituted die assembly are bumps (Fig.2, element #126, paragraph [0010], rows 1-2). Thus, both references Karhade and Yu teach electrical connections formed on a side of the reconstituted die assembly. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the contacts disclosed by Karhade could have been replaced for the bumps disclosed by Yu, because both serve the same purpose of providing electrical connections for dies. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection for connecting the die assembly to circuit boards or power sources. Conductive bumps have low inductance and can be arranged across an entire die surface, enabling high contact densities, and making them suitable for high-speed digital circuits connections.
Regarding claim 12, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. The combination of Wu, Chen and Yu does not teach the method as claimed in claim 1, further comprising providing a second reconstituted die assembly that is similar to the reconstituted die assembly, and bonding the conductive bumps of the reconstituted die assembly to conductive bumps of the second reconstituted die assembly, such combination of the reconstituted die assembly and the second reconstituted die assembly forming the integrated device package. Karhade teaches providing a second reconstituted die assembly that is similar to the reconstituted die assembly (Fig.4, reconstituted die assembly, element #401 is similar to reconstituted die assembly, element #402), and bonding the conductive bumps of the reconstituted die assembly to conductive bumps of the second reconstituted die assembly (Yu teaches bumps as noted in the above rejection of claim 11, and Karhade connecting the die assemblies, Fig.4, elements #440 are bonded to elements #140), such combination of the reconstituted die assembly and the second reconstituted die assembly forming the integrated device package (Fig.4, they from element #400). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Karhade and disclose providing a second reconstituted die assembly that is similar to the reconstituted die assembly, and bonding the conductive bumps of the reconstituted die assembly to conductive bumps of the second reconstituted die assembly, such combination of the reconstituted die assembly and the second reconstituted die assembly forming the integrated device package. This enables multiple dies to be incorporated in the same integrated device package therefore providing a smaller footprint for the package as compared to having the dies disposed laterally, adjacent to one another.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chen, Yu and in view of NG et al., (United States Patent Application Publication Number, US 2012/0119378 A1) hereinafter referenced as NG, and in view of Lu et al., (United States Patent Number, US 8,384,215 B2) hereinafter referenced as Lu.
Regarding claim 15, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection. The combination of Wu, Chen and Yu does not teach the method as claimed in claim 1, wherein preparation of the plurality of dies further comprises the steps of forming multiple through vias filled with a conductive material in each die, and forming the conductive bumps on opposite sides of the through vias, prior to forming the first non-conductive dielectric layer on the first side of each die, the first non-conductive dielectric layer on the first side of each die covering the conductive bumps, for bonding each die to the carrier. NG teaches wherein preparation of the plurality of dies further comprises the steps of forming multiple through vias filled with a conductive material in each die (Fig.6a, die, element #6501 has through vias filled with conductive material, elements #630), and forming the die contacts on opposite sides of the through vias (Fig.6a, elements #633 and #635, paragraph [0075], rows 1-3), prior to forming the first non-conductive layer on the first side of each die (Fig.6a, element #377, paragraph [0077], rows 1-3 is non-conductive since otherwise would short the through vias and the inventions will not work)
NG does not teach the die contacts are conductive bumps. Lu teaches forming multiple through vias filled with a conductive material in each die and forming the conductive bumps on opposite sides of the through vias (Fig.3B, each die has through vias, elements #314, #324, #334 and conductive bumps at opposite sides, elements #312, #322, #332, #316, #326, #336, column 4, rows 27-29). Thus, both references NG and Lu teach electrical connections formed on a side of each die. A person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the die connectors disclosed by NG could have been replaced for the bumps disclosed by Lu, because both serve the same purpose of providing electrical connections for the dies. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an electrical connection for connecting the dies to circuit boards or other dies. Conductive bumps have low inductance and can be arranged across an entire die surface, enabling high contact densities, and making them suitable for high-speed digital circuits connections.
NG further teaches prior to forming the first non-conductive dielectric layer on the first side of each die (Fig.6a, element #377, paragraph [0077], rows 1-3 is non-conductive since otherwise would short the through vias and the inventions will not work), the first non-conductive dielectric layer on the first side of each die covering the conductive bumps, for bonding each die to the carrier (as above Lu discloses the connectors are bumps, and NG in Fig.6b, element #377 covers the conductive connectors, element #635 and is bonded to the carrier, element #380). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of NG and Lu and disclose wherein preparation of the plurality of dies further comprises the steps of forming multiple through vias filled with a conductive material in each die, and forming the conductive bumps on opposite sides of the through vias, prior to forming the first non-conductive dielectric layer on the first side of each die, the first non-conductive dielectric layer covering the conductive contact bumps on the first side of each die for bonding each die to the carrier. As disclosed by NG, the through vias allow direct electrical connections between a wiring substrate and a second die, both connected to the die (Fig.2), which offers flexibility in designing the package. The dielectric layer covering the conductive bumps protects them from damage during processing and allows the attachment of the dies to the carrier.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chen, Yu, NG, Lu and in view of Krishnatreya et al., (United States Patent Application Publication Number, US 2025/0006695 A1) hereinafter referenced as Krishnatreya.
Regarding claim 16, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection and the combination of Wu, Chen, Yu, NG and Lu teaches the method of claim 15 as set forth in the obviousness rejection. The combination of Wu, Chen, Yu, NG and Lu does not teach the method as claimed in claim 15 wherein after forming the reconstituted die assembly, providing a second reconstituted die assembly which is similar to the reconstituted die assembly, and bonding the conductive bumps of the second reconstituted die assembly to the conductive bumps of the reconstituted die assembly. Krishnatreya teaches providing a second reconstituted die assembly (Fig.6B, formed by elements #106-3, #106-4, #180-3 and #130-3; Note that, before connection to the other die assembly, this structure can be connected to a carrier layer, similar to Fig.8D) that is similar to the reconstituted die assembly (Fig.6B, reconstituted die assembly, formed by elements #160-2, #130-2, #180-2, is similar to second reconstituted die assembly), and bonding the conductive bumps of the reconstituted die assembly to conductive bumps of the second reconstituted die assembly (as noted above Lu teaches conductive bumps, Krishnatreya teaches in Fig.6B, the conductive connections of the two assemblies bonded to each other). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Krishnatreya and disclose providing a second reconstituted die assembly that is similar to the reconstituted die assembly and bonding the conductive bumps of the reconstituted die assembly to conductive bumps of the second reconstituted die assembly. This enables multiple similar dies to be incorporated in the same integrated device package and provides a smaller footprint for the package as compared to having the dies disposed laterally, adjacent to one another, on the same wafer.
Claim 17, 18, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Chen, Yu, NG, Lu, Krishnatreya and in view of Lin et al., (United States Patent Number, US 11,121,118 B2) hereinafter referenced as Lin.
Regarding claim 17, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection, the combination of Wu, Chen, Yu NG and Lu teaches the method of claim 15 as set forth in the obviousness rejection and the combination of Wu, Chen, Yu, NG, Lu, and Krishnatreya teaches the method of claim 16 as set forth in the obviousness rejection. The combination of Wu, Chen, Yu, NG, Lu and Krishnatreya does not teach the method as claimed in claim 16, further comprising removing the carrier and a portion of the first non-conductive dielectric layer covering the conductive bumps on the first side of each die of the reconstituted die assembly, in order to expose the conductive bumps on the first side of each die of the reconstituted die assembly that are flush with a top surface of a portion of the first non-conductive dielectric layer covering the conductive bumps on the first side of each die which has not been removed. Lin teaches removing the carrier (Fig.3G to 3I, element #301 is removed) and a portion of the first non-conductive dielectric layer covering the conductive bumps on the first side of each die of the reconstituted die assembly, in order to expose the conductive bumps on the first side of each die of the reconstituted die assembly (part of element #145, made of polyimide, column 3, rows 20-21 and showed in Fig.4 is removed, column 6, rows 55-64) that are flush with a top surface of a portion of the first non-conductive dielectric layer covering the conductive bumps on the first side of each die which has not been removed (Fig.4, element #134 are flush with the top surface of element #145 that has not been removed). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Lin and disclose removing the carrier and a portion of the non-conductive dielectric layer of the reconstituted die assembly, in order to expose the conductive bumps of the reconstituted die assembly that are flush with a top surface of a portion of the non-conductive dielectric layer that remains which has not been removed. Exposing the conductive bumps allows the die to be connected to other dies or external power sources, while providing a planar surface makes it easier to attach redistribution layers or wiring substrates to the surface of the die.
Regarding claim 18, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection, the combination of Wu, Chen, Yu, NG and Lu teaches the method of claim 15 as set forth in the obviousness rejection, the combination of Wu, Chen, Yu, NG, Lu and Krishnatreya teaches the method of claim 16 as set forth in the obviousness rejection and the combination of Wu, Chen, Yu, NG, Lu, Krishnatreya and Lin teaches the method of claim 17 as set forth in the obviousness rejection. Krishnatreya further teaches the method as claimed in claim 17, wherein after exposing the conductive bumps of the reconstituted die assembly (Fig.6B, reconstituted die assembly, formed by elements #160-2, #130-2, #180-2; Note that, before connection to the other die assembly, this structure can be connected to a carrier layer, similar to Fig.8D or as disclosed by Lin) and providing a third reconstituted die assembly which is similar to the reconstituted die assembly (Fig.6B, formed by elements #130-1, #180-1A, #180-1B and #106, Note that, before connection to the other die assembly, this structure can be connected to a carrier layer, similar to Fig.8D or as disclosed by Lin), and bonding the conductive bumps of the third reconstituted die assembly to the conductive bumps of the reconstituted die assembly (as noted above Lu teaches conductive bumps, and Krishnatreya teaches in Fig.6B, the conductive bumps of the two assemblies are bonded). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Krishnatreya and disclose providing a third reconstituted die assembly which is similar to the reconstituted die assembly and bonding the conductive bumps of the third reconstituted die assembly to the conductive bumps of the reconstituted die assembly. This enables multiple dies to be incorporated into the same integrated device package and provides a smaller footprint for the package as compared to having the dies disposed laterally, adjacent to one another and on the same wafer.
Regarding claim 19, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection, the combination of Wu, Chen, Yu, NG and Lu teaches the method of claim 15 as set forth in the obviousness rejection, the combination of Wu, Chen, Yu, NG, Lu and Krishnatreya teaches the method of claim 16 as set forth in the obviousness rejection and the combination of Wu, Chen, Yu, NG, Lu, Krishnatreya and Lin teaches the method of claim 17 as set forth in the obviousness rejection. Krishnatreya further teaches the method as claimed in claim 17, further comprising providing a second plurality of dies mounted onto a second carrier (Fig.8D, elements #114-2a and #1142B are mounted on a second carrier, element #800-2) via a second non-conductive dielectric layer, and bonding the second plurality of dies to electrically connect conductive contacts of the second plurality of dies to the conductive bumps on the first side of each die of the reconstituted die assembly (as noted above Lu teaches conductive bumps, and Krishnatreya teaches in Fig.8E, the second plurality of dies are electrically bonded to the contact bumps of the die assembly, element #804-1 in Fig.8D). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Krishnatreya and disclose providing a second plurality of dies mounted onto a second carrier via a second non-conductive dielectric layer, and bonding the second plurality of dies to electrically connect conductive contacts of the second plurality of dies to the conductive bumps on the first side of each die of the reconstituted die assembly. This enables multiple dies to be incorporated as part of the same integrated device package and provide a smaller footprint for the package as compared to having the dies disposed laterally, adjacent to one another and on the same wafer.
Regarding claim 20, the combination of Wu, Chen and Yu teaches the method of claim 1 as set forth in the obviousness rejection, the combination of Wu, Chen, Yu, NG and Lu teaches the method of claim 15 as set forth in the obviousness rejection, the combination of Wu, Chen, Yu, NG, Lu and Krishnatreya teaches the method of claim 16 as set forth in the obviousness rejection and the combination of Wu, Chen, Yu, NG, Lu, Krishnatreya and Lin teaches the method of claims 17 and 19 as set forth in the obviousness rejection. As noted in the rejection of claim 17, Lin teaches removing the carrier and a portion of the non-conductive dielectric layer of the reconstituted die assembly in order to expose the conductive bumps of the plurality of dies of the reconstituted die assembly that are flush with a surface of a portion of the non-conductive dielectric layer that remains which has not been removed (see rejection of claim 17). Therefore, it would have been obvious to perform the same procedure for the second reconstituted die assembly, because the results would have been predictable. This allows a repetition of the same process step and using the same fabrication tools to expose the conductive bumps, which reduces costs. Therefore, Lin teaches the method further comprising the steps of: removing a carrier and a portion of a non-conductive dielectric layer of the second reconstituted die assembly in order to expose the conductive bumps of a plurality of dies of the second reconstituted die assembly that are flush with a surface of a portion of the non-conductive dielectric layer which has not been removed.
Krishnatreya further teaches removing the second carrier to expose a surface of the second plurality of dies (Fig.8D and 8E the carriers are removed); wherein such combination of the reconstituted die assembly, the second reconstituted die assembly and the second plurality of dies forms the integrated device package (Fig.8E element #100). Krishnatreya does not teach a second non-conductive dielectric layer between the carrier and the dies. Chen teaches a non-conductive dielectric layer between the carrier and the dies (see rejection of claim 1). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Krishnatreya and Chen and disclose removing the second carrier and second non-conductive dielectric layer to expose a surface of the second plurality of dies. Removing the carrier and the dielectric layer exposes the conductive contact pads, which allows connecting the dies to a circuit board to provide power and signals to the dies (Krishnatreya, Fig.1).
Response to Arguments
Applicant’s arguments filed on 07/30/2026 have been fully considered but they
are not persuasive.
On page 11 of the Applicant Arguments/Remarks document filed on 07/30/2026, the applicant argues that in Wu, “although an adhesive (118) is applied to a backside of each
integrated circuit die (50A, 50B) (paragraph [0032] of Wu), there is no further die preparation on an opposite side of the integrated circuit die (50A, 50B). The integrated circuit dies (50A, 50B) are bonded onto the carrier substrate (102) without such die preparation (FIG. 5 and paragraph [0031] of Wu).”
Wu teaches forming a plurality of die connectors, on a second side of each die opposite to the first side, before bonding to the carrier (Fig.1, elements #66, paragraph [0017], rows 8-10 are formed on the top side of each die before bonding. Note the element #68 may not be present on the top side of the dies, paragraph [0019], rows 1-2), which is part of die preparation. When the dies are bonded to the carrier, as shown in Fig.5, the die connectors are already there. While Wu does not explicitly teach the die connectors are conductive bumps, Yu teaches conductive bumps on a second side of each die opposite the first side (Fig.2, element #126, paragraph [0010], rows 1-2), Therefore, one skilled in the art, would have been able to substitute the die connectors disclosed by Wu with the conductive bumps disclosed by Yu.
On pages 12 and 13 of the Applicant Arguments/Remarks document, filed on 07/30/2026, the applicant argues that “Wu on the other hand discloses forming a unique semiconductor package (100A, 100B, 800A, 800B) after which each semiconductor package is immediately singulated (paragraphs [0046] and [0103] of Wu). Wu does not teach collectively electrically connecting a plurality of dies that otherwise would have to be individually bonded onto an external device like in the prior art”.
As noted in the rejection of claim 1, Wu teaches each region #100A and #100B, comprises a plurality of dies and therefore each region forms a die assembly, in which the plurality of dies are arranged as a single assembly (Fig.7, the plurality of dies in region #100A form a single assembly), configured to collectively electrically connect the conductive bumps of the plurality of dies to an external electronic device (Fig.7, the conductive bumps of the plurality of dies are exposed and therefore are configured to be connect to an external electronic device).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
