DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election of Invention I (claims 1-17) and Species 2 (claims 1 and 4-17) in the reply filed on 07/02/2026 is acknowledged. Because Applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 21-23 have been newly added. Accordingly, claims 1, 4-17, and 21-23 are pending in this application.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 7 and 11-12 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 11 and 14-15 of copending Application No. 19/287,673 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because all the limitations recited in claims 1, 7 and 11-12 of the present invention are recited within claims 1, 11 and 14-15 of copending Application No. 19/287,673.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Application No. 18/505,257 (present invention).
Copending Application No. 19/287,673 (reference).
Claim 1: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor comprising: a first gate; a first source region on a first side of the first gate; a drain region on a second side of the first gate, wherein the second side is opposite the first side; a first spacer surrounding the first gate, wherein the first spacer comprises: a first portion on the first side of the first gate, wherein the first portion has a top surface substantially coplanar with a top surface of the first gate, and a second portion on the second side of the first gate, wherein the second portion comprises a first horn structure extending above the top surface of the first gate (see claim 1 of copending Application No. 19/287,673, “a first source/drain (S/D) region” and “a second S/D region” of copending Application No. 19/287,673 have the same meaning and function as “a first source region” and “a drain region” as recited in claim 1 of the present invention).
Claim 1: “A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor comprising: a first gate; a first source/drain (S/D) region on a first side of the first gate; a second S/D region on a second side of the first gate, wherein the second side is opposite the first side; a first spacer surrounding the first gate, wherein the first spacer comprises: a first portion on the first side of the first gate, wherein the first portion has a top surface substantially coplanar with a top surface of the first gate, and a second portion on the second side of the first gate, wherein the second portion comprises a first horn structure extending above the top surface of the first gate”.
Claim 7: the LDMOS transistor of claim 1, wherein the first horn structure comprises a single material (see claim 1, lines 14-15 of copending Application No. 19/287,673, it recites “a first horn structure” which is considered a single structure/body, thus it inherently comprises a single material, as claimed).
Claim 1: “…the second portion comprises a first horn structure…”.
Claim 11: A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor comprising:
a first gate; a second gate; a drain region between the first gate and the second gate (see claim 1, lines 1-6 of copending Application No. 19/287,673),
wherein each of the first gate and the second gate is usable to control a voltage at the drain region (see claim 1, lines 6-8 of copending Application No. 19/287,673);
a first spacer surrounding the first gate (see claim 1, line 8 of copending Application No. 19/287,673),
wherein the first spacer comprises: a first portion on a side of the first gate closest to the drain region, wherein the first portion comprises a first horn structure extending above a top surface of the first gate (see claim 11, lines 8-13 of copending Application No. 19/287,673);
and a second spacer surrounding the second gate (see claim 14 of copending Application No. 19/287,673),
wherein the second spacer comprises: a second portion on a side of the second gate closest to the drain region, wherein the second portion comprises a second horn structure extending above a top surface of the second gate (see claim 15 of copending Application No. 19/287,673, “the S/D region” of copending Application No. 19/287,673 has the same meaning and function as “the drain region” as recited in claim 11 of the present invention).
Claims 11, 14 and 15: “A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor comprising:
a first gate; a second gate; a source/drain (S/D) region between the first gate and the second gate,
wherein each of the first gate and the second gate is usable to control a voltage at the S/D region;
a first spacer surrounding the first gate,
wherein the first spacer comprises: a first portion on a side of the first gate closest to the S/D region, wherein the first portion comprises a first horn structure extending above a top surface of the first gate” (claim 11);
“a second spacer surrounding the second gate…” (claim 14) ;
“wherein a second portion of the second spacer on a side of the second gate closest to the S/D region comprises a second horn extending above a top surface of the second gate” (claim 15).
Claim 12: the LDMOS transistor of claim 11, wherein at least one of the first horn structure or the second horn structure has a tapered shape (see claims 11 and 15 of copending Application No. 19/287,673, “a first horn structure” or “a second horn” inherently has a tapered shape because it naturally narrows from a wide base to a pointed tip).
Claims 11 and 15: “wherein the first portion comprises a first horn structure extending above a top surface of the first gate” (claim 11, lines 12-14)…and “a second portion of the second spacer …comprises a second horn extending above a top surface of the second gate” (claim 15).
Claims 4-6 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 19/287,673 in view of CHEN et al. (U.S 2022/0085038 A1).
This is a provisional nonstatutory double patenting rejection.
As to claim 4, as applied to claim 1 above, claim 1 of copending Application No. 19/287,673 disclose/recite all claimed limitations, except for the limitation: wherein the first spacer comprises: a first silicon oxide layer; a silicon nitride layer over the first silicon oxide layer; and a second silicon oxide layer over the silicon nitride layer.
However, CHEN et al. disclose in Fig. 7A a transistor comprising: a first spacer (630) comprises: a first silicon oxide layer (632); a silicon nitride layer (634) over the first silicon oxide layer (632); and a second silicon oxide layer (636) over the silicon nitride layer (634) (see Fig. 7B, para. [0083]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the claim of copending Application No. 19/287,673 to include a first spacer comprising a first silicon oxide layer, a silicon nitride layer over the first silicon oxide layer; and a second silicon oxide layer over the silicon nitride layer as taught by CHEN et al., in order to improve charge retention, minimize leakage current, and enhance the reliability of the transistor by effectively trapping charge within the oxide-nitride-oxide (ONO) stack.
As to claim 5, as applied to claim 1 above, claim 1 of copending Application No. 19/287,673 disclose/recite all claimed limitations, except for the limitation: wherein the first spacer comprises: a silicon oxide layer; and a silicon nitride layer over the silicon oxide layer.
However, CHEN et al. disclose in Fig. 7A a transistor comprising: a first spacer (630) comprises: a silicon oxide layer (632); and a silicon nitride layer (634) over the silicon oxide layer (632) (see Fig. 7B, para. [0083]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the claim of copending Application No. 19/287,673 to include a first spacer comprising a silicon oxide layer; and a silicon nitride layer over the silicon oxide layer as taught by CHEN et al., in order to improve charge retention, minimize leakage current, and enhance the reliability of the transistor.
As to claim 6, as applied to claim 1 above, claim 1 of copending Application No. 19/287,673 disclose/recite all claimed limitations, except for the limitation: wherein the first spacer comprises: a silicon nitride layer; and a silicon oxide layer over the silicon nitride layer.
However, CHEN et al. disclose in Fig. 7A a transistor comprising: a first spacer (630) comprises: a silicon nitride layer (634), and a silicon oxide layer (636) over the silicon nitride layer (634) (see Fig. 7B, para. [0083]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the claim of copending Application No. 19/287,673 to include a first spacer comprising a silicon nitride layer; and a silicon oxide layer over the silicon nitride layer as taught by CHEN et al., in order to improve charge retention, minimize leakage current, and enhance the reliability of the transistor.
Allowable Subject Matter
Claims 8-10, and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-23 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: a lateral diffusion metal-oxide-semiconductor (LDMOS) transistor comprising:
a first spacer surrounding the first gate, wherein the first spacer comprises: a first portion on the first side of the first gate, wherein the first portion has a top surface substantially coplanar with a top surface of the first gate, and a second portion on the second side of the first gate, wherein the second portion comprises a first horn structure extending above the top surface of the first gate; and a silicide layer over the top surface of the first gate, wherein the silicide layer extends across an entirety of the top surface of the first gate, in combination with other claimed features, as recited in independent claim 21. Claims 22-23 are dependent upon independent claim 21 and are also allowed.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Thanh Y. Tran/Primary Examiner, Art Unit 2817 September 17, 2026
Prosecution Insights