DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed on pages 8 and 9 of the remarks filed on 8/4/2026 with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Majhi et al. (20230138658) in view of Lee (20170345945)
Regarding Claim 1, in Figs. 1A and 1B, Majhi et al. discloses a semiconductor device comprising: a substrate 102; an active pattern 110 extended in a first horizontal direction on the substrate; a plurality of nanosheets 118a/118b stacked and spaced apart from each other in a vertical direction on the active pattern; a gate electrode 132 extended in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets 118a/118b; a source/drain region 106/108 on both sides of the plurality of nanosheets in the first horizontal direction on the active pattern; a gate insulating layer 120 between the plurality of nanosheets and the gate electrode; and a doping layer 118c between the plurality of nanosheets 118a/118b and the gate insulating layer 120, the doping layer including silicon (Si) or silicon germanium (SiGe), and the doping layer doped with a doping material (see paragraphs 0041 and 0100), at least a portion of the doping layer overlapping an uppermost nanosheet 118 of the plurality of nanosheets 118a/118b in the first horizontal direction. Majhi et al. fails to disclose the newly added limitation where a gate spacer on both the first and second sidewalls of the gate electrode in the horizontal direction and on an upper surface of an uppermost nanosheet of the plurality of nanosheets, the gate spacer in contact with the upper surface of the uppermost nanosheet of the plurality of nanosheets, an upper surface of the gate spacer being higher than an upper surface of the source/drain region. However, Lee et al. discloses a semiconductor device where in Fig. 1 and paragraphs 0042, 0088, 0089 and 0090, such gate spacer 140 and source/drain regions 150 are disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required gate spacers in Majhi as taught by Lee et al to protect the gates.
Regarding Claim 2, in Majhi, at least a portion of a sidewall of the doping layer 118c in the first horizontal direction is in contact (albeit indirectly) with the uppermost nanosheet 118b of the plurality of nanosheets 118b/118a.
Regarding Claim 3, in Majhi an uppermost surface of the doping layer 118c is formed on the same plane as an upper surface of the uppermost nanosheet 118b of the plurality of nanosheets 118a/118b
Regarding Claim 4, in Majhi at least a portion of the doping layer 118c is in contact (albeit indirectly) with the active pattern 110.
Regarding Claim 5, in Majhi substrate 102 is defined as a PMOS region, and the doping material is an n-type doping material (see paragraphs 0040, 0064 and 0099).
Regarding Claim 6, in Majhi substrate 102 is defined as an NMOS region, and the doping material is a p-type doping material (see paragraphs 0040, 0064 and 0099)
Regarding Claim 7, in Majhi at least a portion of the doping layer 118c is between the source/drain region 106/108 and the gate insulating layer 120.
Regarding Claim 8, in Majhi at least a portion of the doping layer 118c is in contact (albeit indirectly) with the source/drain region 106/108.
Regarding Claim 9, in Majhi an inner spacer 135 on both sidewalls of the gate electrode in the first horizontal direction between the plurality of nanosheets, the inner spacer being in contact with the source/drain region 106/108 and each of the plurality of nanosheets 118a/118b.
Regarding Claim 10, in Majhi a thickness of a lowermost nanosheet 118a of the plurality of nanosheets 118a/118b in the vertical direction in a portion that is in contact with the source/drain region 106/108 is greater than a thickness of the lowermost nanosheet 118a of the plurality of nanosheets 118a/118b in the vertical direction in a portion between the doping layers (see Figs 1C, 1D, 4B and 6).
Regarding Claim 11, in Majhi at least a portion of a sidewall of the doping layer 118c in the first horizontal direction is in contact (albeit indirectly) with a lowermost nanosheet 118a of the plurality of nanosheets 118a/118b.
Regarding Claim 12, in Majhi at least a portion of a sidewall of the doping layer 118c in the first horizontal direction is in contact (albeit indirectly) with the active pattern
Regarding Claim 13, in Figs. 5A, 5B and 6, Majhi et al. discloses a semiconductor device comprising: a substrate 102 in which an NMOS region and a PMOS region are defined (see paragraphs 0040, 0064 and 0099) ; a first active pattern 410 extended in a first horizontal direction on the NMOS region of the substrate; a second active pattern 410 extended in the first horizontal direction on the PMOS region of the substrate; a first plurality of nanosheets 423a/423b stacked and spaced apart from each other in a vertical direction on the first active pattern; a second plurality of nanosheets 423a/423b stacked and spaced apart from each other in the vertical direction on the second active pattern; a first gate electrode 432 extended in a second horizontal direction different from the first horizontal direction on the first active pattern, the first gate electrode surrounding the first plurality of nanosheets 423a/423b; a second gate electrode extended 432 in the second horizontal direction on the second active pattern, the second gate electrode 432 surrounding the second plurality of nanosheets 423a/423b; a first source/drain region 406/408 on both sides of the first plurality of nanosheets in the first horizontal direction on the first active pattern; a second source/drain region 406/408 on both sides of the second plurality of nanosheets in the first horizontal direction on the second active pattern; a first gate insulating layer 420 between the first plurality of nanosheets and the first gate electrode; a second gate insulating layer 420 between the second plurality of nanosheets and the second gate electrode; and a first doping layer 423c between the second plurality of nanosheets 423a/423b and the second gate insulating layer 420, the first doping layer 423c including silicon (Si) or silicon germanium (SiGe), the first doping layer doped with an n-type doping material (see Table 1, paragraphs 0119-0123), at least a portion of the first doping layer overlapping an uppermost nanosheet 423b of the second plurality of nanosheets 423a/423b in the first horizontal direction.
Majhi et al. fails to disclose the newly added limitation where a gate spacer on both the first and second sidewalls of the gate electrode in the horizontal direction and on an upper surface of an uppermost nanosheet of the plurality of nanosheets, the gate spacer in contact with the upper surface of the uppermost nanosheet of the plurality of nanosheets, an upper surface of the gate spacer being higher than an upper surface of the source/drain region. However, Kim et al. discloses a semiconductor device where in Figs. 1-10 and paragraphs 0022 and 0061-0065, such gate spacer 130 and source/drain regions 140 are disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required gate spacers in Majhi as taught by Kim et al to protect the gates.
Regarding Claim 14, in Majhi, at least a portion of the first doping layer 423c is between the second source/drain region 406/408 and the second gate insulating layer 420.
Regarding Claim 15, in Majhi, a first inner spacer 435 on both sidewalls of the first gate electrode 432 in the first horizontal direction between the first plurality of nanosheets 423a/423b, the first inner spacer 435 being in contact with the first source/drain region 406/408and each of the first plurality of nanosheets 423a/423b.
Regarding Claim 16, in Majhi, a second inner spacer 435 on both sidewalls of the second gate electrode 432 in the first horizontal direction between the second plurality of nanosheets 423a/423b, the second inner spacer being 435 in contact (albeit indirectly) with the second source/drain region 406/408 and each of the second plurality of nanosheets 423a/423b.
Regarding Claim 17, in Majhi, a second doping layer 423c (for example side portions) between the first plurality of nanosheets 423a/423b and the first gate insulating layer 420, the second doping layer including silicon (Si) or silicon germanium (SiGe), the second doping layer doped with a p-type doping material, at least a portion of the second doping layer overlapping an uppermost nanosheet 423b of the first plurality of nanosheets 423a/423b in the first horizontal direction.
Regarding Claim 18, in Majhi, in Figs. 5A, 5B and 6, Majhi et al. discloses a semiconductor device comprising: a substrate 402 in which an NMOS region and a PMOS region are defined; a first active pattern 410 extended in a first horizontal direction on the NMOS region of the substrate; a second active pattern 410 extended in the first horizontal direction on the PMOS region of the substrate ((see paragraphs 0040, 0064 and 0099); a first plurality of nanosheets 423a/423b stacked and spaced apart from each other in a vertical direction on the first active pattern; a second plurality of nanosheets 423a/423b stacked and spaced apart from each other in the vertical direction on the second active pattern; a first gate electrode 432 extended in a second horizontal direction different from the first horizontal direction on the first active pattern, the first gate electrode surrounding the first plurality of nanosheets; a second gate 432 electrode extended in the second horizontal direction on the second active pattern, the second gate electrode 432 surrounding the second plurality of nanosheets; a first source/drain region 406/408 on both sides of the first plurality of nanosheets in the first horizontal direction on the first active pattern; a second source/drain region 406/408 on both sides of the second plurality of nanosheets in the first horizontal direction on the second active pattern; a first gate insulating layer 420 between the first plurality of nanosheets 423a/423b and the first gate electrode 432; a second gate insulating layer 420 between the second plurality of nanosheets 423a/423b and the second gate electrode 432; and a first doping layer 423c between the first plurality of nanosheets and the first gate insulating layer, the first doping layer 423c including silicon (Si) or silicon germanium (SiGe), the first doping layer doped with a p-type doping material (see Table 1, paragraphs 0119-0123), at least a portion of the first doping layer 423c overlapping an uppermost nanosheet of the first plurality of nanosheets 423a/423b in the first horizontal direction. Majhi et al. fails to disclose the newly added limitation where a gate spacer on both the first and second sidewalls of the gate electrode in the horizontal direction and on an upper surface of an uppermost nanosheet of the plurality of nanosheets, the gate spacer in contact with the upper surface of the uppermost nanosheet of the plurality of nanosheets, an upper surface of the gate spacer being higher than an upper surface of the source/drain region. However, Kim et al. discloses a semiconductor device where in Figs. 1-10 and paragraphs 0022 and 0061-0065, such gate spacer 130 and source/drain regions 140 are disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required gate spacers in Majhi as taught by Kim et al to protect the gates.
Regarding Claim 19, in Majhi, at least a portion of the first doping layer 423c is between the first source/drain region 406/408 and the first gate insulating layer 420.
Regarding Claim 20, in Majhi, a second doping layer 423c (for example side portions of 423c) between the second plurality of nanosheets 423a/423b and the second gate 432 insulating layer, the second doping layer 423c including silicon (Si) or silicon germanium (SiGe), the second doping layer doped with an n-type doping material (see Table 1, paragraphs 0119-0123), at least a portion of the second doping layer 423c overlapping an uppermost nanosheet 423b of the second plurality of nanosheets 423a/423b in the first horizontal direction.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 10/8/2026
