DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This final office action is responsive to Applicants' response filed on 03/02/26. Claims 1-25 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 10/06/25 has been entered.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-7, 9-11, 13, 15-16, 19-20 and 22-24 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Goswami et al. (EP 4113814 A1 and hereinafter as Gos)
Regarding claim 1. Gos teaches a circuit [fig 3-6], comprising: a multiphase current source, including: a first current loop [first 525-1] configured to drive a first inductor [i.e. first phase] with a first drive signal [170-1] at a first switching frequency [¶121, controller uses PFM and PWM], wherein the first current loop is configured to control trailing edge modulation of the first drive signal based on a first current share error [output of 525] of the first current loop [The output of 525 and the feedback signal is configured to dynamically influence the output characteristics of the output signal of 145 which produces the controlled trailing edge. Thus, having the trailing edge setting based on the current error signal. ¶376];
a second current loop [implicit from 525-2, ¶121] configured to drive a second inductor [i.e. second phase] with a second drive signal [170-2] at a second switching frequency; and a voltage loop [141 w/ 526] comprising a constant on-time (COT) control stage configured to provide a control signal with a leading edge modulation [¶366] based on voltage error [same rational as above the output of 145 is dynamically adjusted based on all feedback inputs ].
Regarding claim 5. Gos teaches the circuit of claim 1, wherein the COT control stage includes a trigger ramp signal [fig 13, 1320-X].
Regarding claim 6. Gos teaches the circuit of claim 1, wherein the COT control stage is configured to provide trigger pulses that are out of phase with one another [i.e. output of 145 has a variable frequency].
Regarding claim 7. Gos teaches the circuit of claim 1, wherein at least one of the first current loop and the second current loop of the multiphase current source is implemented as a masterless current share [this is interpreted as achieving function of circuit without adding complexity, thus, Gos is interpreted as performing function without adding unwanted complexity] loop configured to provide a trailing edge current error correction [reset signal to OFF high switch], wherein a gain of the masterless current share loop is dynamically adjustable based on an error signal level [output of 145 is dynamically adjusted based on all feedback inputs].
Regarding claim 9. Gos teaches the circuit of claim 7, wherein a gain of the masterless current share loop is part of a Ton ramp [gmr is part of the ramp circuit].
Regarding claim 10. Gos teaches the circuit of claim 9, wherein a gain of the masterless current share loop [i.e. iL is adjustable per controller’s adjustments] is adjustable by changing a height of the Ton ramp.
Regarding claim 11. Gos teaches the circuit of claim 1, configured as a buck voltage regulator circuit in which an output voltage is less than an input voltage [¶51].
Regarding claim 13. Gos teaches the circuit of claim 1, configured as a boost voltage regulator circuit in which an output voltage is greater than an input voltage [claim rejected base on original presentation, election species do not show a boost].
Regarding claim 15. Gos teaches a method [method by fig 3-6] of regulating a voltage, the method comprising: performing a DC-to-DC voltage conversion in a multiphase current source [see fig 3, ¶48] coupled to a dynamic load [¶118], the multiphase current source including a plurality of phases;
providing an output current from the multiphase current source [see 149]; varying a pulse frequency [¶121, controller uses PFM and PWM] in response to a change in a load current of the dynamic load;
varying a pulse width in response to the change in the load current, to provide adaptive on-time control [¶97]; increasing the output current to match the load current [function of device of fig 3]; and producing an output voltage signal having zero undershoot [it is understood the voltage remains above zero voltage to power the load], wherein providing the output current includes a masterless current balance [function of 525] procedure including independently controlling trailing edge modulation within each of the plurality of phases based on a respective current share error of a respective current loop [The output of 525 and the feedback signal is configured to dynamically influence the output characteristics of the output signal of 145 which produces the controlled trailing edge. Thus, having the trailing edge setting based on the current error signal. ¶376].
Regarding claim 16. Gos teaches the method of claim 15, wherein the response to the change in the load current includes supplying the output current in increasing steps [inductor current changes in steps per function of controller].
Regarding claim 19. Gos teaches a system [fig 3-6], comprising: a power delivery circuit configured to deliver power to a dynamic load [function of device of fig 3], the power delivery circuit including: a voltage regulator having an input voltage [Vin], an output voltage [Vout], and an output capacitance [Co]; and a constant on-time (COT) control stage [fig 5-6, 526] configured to provide variable on-time in response to a change in the dynamic load [function of circuit in fig 3]; a first current loop [first 525-1] configured to drive a first inductor [i.e. first phase] with a first drive signal [170-1] at a first switching frequency [¶121, controller uses PFM and PWM], wherein the first current loop is configured to control trailing edge modulation of the first drive signal based on a first current share error of the first current loop [The output of 525 and the feedback signal is configured to dynamically influence the output characteristics of the output signal of 145 which produces the controlled trailing edge. Thus, having the trailing edge setting based on the current error signal. ¶376]; and a second current loop [implicit from 525-2, ¶121] configured to drive a second inductor [i.e. 2nd phase] with a second drive signal at a second switching frequency [170-2].
Regarding claim 20. Gos teaches the system of claim 19 wherein the voltage regulator is configured to provide an output voltage signal with zero undershoot [it is understood the voltage remains above zero voltage to power the load].
Regarding claim 22. Gos teaches the system of claim 19, further comprising a multiphase current source system configured with adjustable current share gain [i.e. multiphase circuit that adjusts inductor current].
Regarding claim 23. Gos teaches the system of claim 19, wherein the second current loop is configured to control trailing edge modulation of the second drive signal based on a second current share error of the second current loop [output of 145, which controllers the second phase current, is dynamically adjusted based on all feedback inputs].
Regarding claim 24. Gos teaches the circuit of claim 1, wherein the second current loop is configured to control trailing edge modulation of the second drive signal based on a second current share error of the second current loop [output of 525 is dynamically adjusted based on all feedback inputs].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 rejected under 35 U.S.C. 103 as being unpatentable over Gos et al. in view of Cheng et al. (US 20190190386 A1)
Regarding claim 2. Gos teaches the circuit of claim 1.
While Gos teaches the first drive signal is out of phase with the second drive signal [implicit since the phases are at different by variable frequency control of switching frequencies]. However, Gos does not explicitly mention a circuit wherein the first drive signal and the second drive signal are pulse width modulation (PWM) drive signals. Cheng teaches a circuit wherein the first drive signal and the second drive signal are pulse width modulation (PWM) drive signals [¶19].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Cheng in order to provide fixed frequency which makes it easier to filter and manage EMI noise levels.
Regarding claim 3. Gos as modified teaches the circuit of claim 2, wherein an output voltage signal is configured to have a zero undershoot response when the multiphase current source is coupled to a dynamic load [fig 30, shows that Vc maintains target voltage without dipping below the target voltage].
Claim 4 rejected under 35 U.S.C. 103 as being unpatentable over Gos et al. in view of Li (US 20210320582 A1)
Regarding claim 4. Gos teaches the circuit of claim 1. However, Gos does not explicitly mention a circuit wherein the COT control stage includes an integrator. Li teaches wherein the COT control stage [stage shown in fig 2] includes an integrator [i.e. integrator shown in ¶17].
Claim 14 rejected under 35 U.S.C. 103 as being unpatentable over Gos et al. in view of Xue (US 20190068046 A1)
Regarding claim 14. Gos teaches the circuit of claim 1.
However, Gos does not explicitly mention a circuit wherein a footprint of the circuit is less than about 25 mm2. Xue teaches wherein a footprint of the circuit is less than about 25 mm2 [¶33, imply reducing die area]. Since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Xue in order to modify a specific die area value which would better align the circuit towards design requirements.
Claims 12 and 21 rejected under 35 U.S.C. 103 as being unpatentable over Gos et al.
Regarding claim 12. Gos teaches the circuit of claim 11, except for wherein the input voltage is in a range of about 5 V to about 21 V and the output voltage is in a range of about 0.2 V to about 3.3 V. Since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify a specific threshold value which would better align the circuit towards design requirements.
Regarding claim 21. Gos teaches the system of claim 20, wherein the output voltage signal remains stable when the output capacitance is less than 1 mF [¶56 shows that Co has a capacitance to keep regulation stable]. Since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify a specific threshold value which would better align the circuit towards design requirements.
Allowable Subject Matter
Claim 25 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838
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