DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 8 July 2026 of Applicants’ amendments in which claims 1, 5, 6, 16, and 20 are amended, claims 2-4, 10-15, and 17-19 are cancelled, and claims 21 and 22 are newly added. The Office withdraws the drawing objection and section 112(b) rejections identified in the Office Communication dated 8 April 2026 in view of the amendments.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5-9, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, line 13, recites “affixing a copper pillar affixed to the bond pad,” which is indefinite because it is unclear how a thing previously affixed is re-affixed to the same thing. For the purposes of clarity and compact prosecution, this will be interpreted as “affixing a copper pillar to the bond pad.”
Claim 1, lines 14-16, recites “mounting the second semiconductor die in the first cavity by inserting the copper pillar into the second cavity and the second semiconductor die into the first cavity,” which is indefinite because it is unclear how a mounting of a thing necessarily occurs by inserting two things into separate cavities. For the purposes of clarity and compact prosecution, this will be interpreted as “inserting the copper pillar into the second cavity and the second semiconductor die into the first cavity and mounting the second semiconductor die in the first cavity.”
Claims 5-9 and 21 are rejected due to their dependence from base claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-9, 16, and 20-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oganesian et al. (US20180130746A1) in view of Aldrete et al. (US20140159238A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejections, Oganesian teaches in Figs. 1 and 3-5 a method comprising:
forming a first cavity (36) in a backside (side of 26) of a first semiconductor die (20), the first semiconductor die (20) having a back end of line (BEOL) region (region of 30, 32, and/or 24), a front end of line (FEOL) region (region of 38; Figs. 3, 4), and a bulk region (region of 22) {[0029, 0030]};
forming a second cavity (48/50) in the backside (side of 26) of the first semiconductor die (20), the second cavity (48/50) beginning at a bottom side (upper portion of 36) of the first cavity (36), extending vertically through the FEOL region (region of 38), and ending at an interconnect (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {Figs. 1, 3, 4; [0032]};
dispensing a thermal compression non-conductive paste (TCNCP) material (44 and/or 86) at the bottom side (upper portion of 36) of the first cavity (36) {[0040, 0042, 0043]};
providing a second semiconductor die (70), the second semiconductor die (70) including a bond pad (84) {Figs. 1, 3, 4; [0033]};
affixing a copper pillar (54) to the bond pad (84) of the second semiconductor die (70) {Figs. 1, 3, 4; [0033]};
inserting the copper pillar (54) into the second cavity (48/50) and the second semiconductor die (70) into the first cavity (36) and mounting the second semiconductor die (70) in the first cavity (36) and applying a compressive force (e.g., gravity) between the second semiconductor die (70) and the first semiconductor die (20), and causing a tip of the copper pillar (54) to be placed into electrical contact with an interconnect trace (56) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) (Figs. 1, 5; [0038]}.
Oganesian does not teach affixing the copper pillar to the second semiconductor die before: inserting the copper pillar into the second cavity and the second semiconductor die into the first cavity, mounting the second semiconductor die in the first cavity, and applying a compressive force between the second semiconductor die and the first semiconductor die to displace the TCNCP material to cause a tip of the copper pillar to be placed into electrical contact with an interconnect trace.
In an analogous art, Aldrete teaches in Figs. 2 and 3 and paragraphs [0004-0006] operations of affixing a copper pillar (205) to a semiconductor die (208) and thereafter: (1) inserting the copper pillar (205) into a cavity so as to mount the semiconductor die (208) and (2) applying a compressive force to the semiconductor die (208) to displace the TCNCP material (201) and to cause a tip of the copper pillar (205) to be placed into electrical contact with an interconnect trace (203). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oganesian’s method based on the teachings of Aldrete, to achieve the above-identified subject matter, because thermal compression bonding processes are generally more accurate. Aldrete [0002]. Moreover, applying a known technique (e.g., as taught by Aldrete) in the same way to enhance another known technique (e.g., as taught by Oganesian) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Consequences of applying Aldrete’s teachings to those of Oganesian are that: (a) Oganesian’s second semiconductor die is inserted into Oganesian’s first cavity and mounted therein after affixing the copper pillar to the bond pad of Oganesian’s second semiconductor die, (b) a compressive force is applied between Oganesian’s first and second semiconductor dies, and (c) the tip of Oganesian’s copper pillar is caused to be placed into electrical contact with an interconnect trace of the BEOL region of Oganesian’s semiconductor die.
Regarding claim 5, Oganesian as modified by Aldrete teaches the method of claim 1, and Oganesian further teaches wherein the TCNCP material (44 and/or 86) at least partially fills a gap region between sidewalls of the second semiconductor die (70) and sidewalls of the first cavity (36) after mounting the second semiconductor die (70) in the first cavity (36) {Figs. 1, 6; [0040]}.
Regarding claim 6, Oganesian as modified by Aldrete teaches the method of claim 1, and Oganesian further teaches wherein mounting the second semiconductor die (70) in the first cavity (36) further comprises applying the compressive force (e.g., gravity/load or bonding) between the second semiconductor die (70) and the first semiconductor die (20) to interconnect the second semiconductor die (70) with the interconnect trace (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {[0034, 0042]}.
Regarding claim 7, Oganesian as modified by Aldrete teaches the method of claim 1, and Oganesian further teaches wherein forming the first cavity (36) in the backside (side of 26) of the first semiconductor die (20) includes forming the first cavity (36) by way of a dry etch (e.g., sandblasting) {[0045]}.
Regarding claim 8, Oganesian as modified by Aldrete teaches the method of claim 1, and Oganesian further teaches wherein a backside (side of 76) of the second semiconductor die (70) and the backside (side of 26) of the first semiconductor die (20) are substantially coplanar after mounting the second semiconductor die (70) in the first cavity (36) {Fig. 1; [0009]}.
Regarding claim 9, Oganesian as modified by Aldrete teaches the method of claim 1, and Oganesian further teaches further comprising affixing a plurality of conductive package connectors (34, 60, and/or 62) at an active side (side of 24) of the first semiconductor die (20) {Fig. 1; [0029, 0035]}.
Regarding claim 16, Oganesian teaches in Fig. 1 a method comprising:
forming a first cavity (36) in a backside (side of 26) of a first semiconductor die (20), the first semiconductor die (20) having a back end of line (BEOL) region (region of 30, 32, and/or 24), a front end of line (FEOL) region (region of 38; Figs. 3, 4), and a bulk region (region of 22) {[0029, 0030]};
forming a second cavity (48/50) in the backside (side of 26) of the first semiconductor die (20), the second cavity (48/50) beginning at a bottom side (upper portion of 36) of the first cavity (36), extending vertically through the FEOL region (region of 38), and ending at an interconnect trace (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {Figs. 1, 3, 4; [0032]};
dispensing a thermal compression non-conductive paste (TCNCP) material (44 and/or 86) at the bottom side of the first cavity (upper portion of 36) {[0040, 0042, 0043]};
affixing a conductive pillar (54) to a bond pad (84) of a second semiconductor die (70) {Figs. 1, 3, 4; [0033]}; and
inserting the copper pillar (54) into the second cavity (48/50) and the second semiconductor die (70) into the first cavity (36) and mounting the second semiconductor die (70) in the first cavity (36) to cause a tip of the conductive pillar (54) to be placed into electrical contact with the interconnect trace (56) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) (Figs. 1, 5; [0038]}.
Oganesian does not teach: (I) dispensing a thermal compression non-conductive paste (TCNCP) material at the bottom side of the first cavity before mounting the second semiconductor die in the first cavity and (II) affixing the conductive pillar before mounting the second semiconductor die in the first cavity to insert the conductive pillar into the second cavity to displace the TCNCP material to cause a tip of the conductive pillar to be placed into electrical contact with the interconnect trace.
Aldrete teaches in Figs. 2 and 3 and paragraphs [0004-0006] operations of: (1) dispensing a thermal compression non-conductive paste (TCNCP) material (201) at the bottom side of a cavity before mounting a semiconductor die (208) in the cavity and (2) affixing a conductive pillar (205) to a semiconductor die (208) before mounting the semiconductor die (208) to insert the conductive pillar (205) into the cavity to displace the TCNCP material (201) to cause a tip of the conductive pillar (205) to be placed into electrical contact with an interconnect trace (203). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oganesian’s method based on the teachings of Aldrete, to achieve the above-identified subject matter, because thermal compression bonding processes are generally more accurate. Aldrete [0002]. Moreover, applying a known technique (e.g., as taught by Aldrete) in the same way to enhance another known technique (e.g., as taught by Oganesian) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C). Consequences of applying Aldrete’s teachings to those of Oganesian are that: (a) Oganesian’s second semiconductor die is mounted in Oganesian’s first cavity and (b) the tip of Oganesian’s copper pillar is caused to be placed into electrical contact with an interconnect trace of the BEOL region of Oganesian’s semiconductor die.
Regarding claim 20, Oganesian as modified by Aldrete teaches the method of claim 16, and Oganesian further teaches wherein the TCNCP material (44 and/or 86) at least partially fills a gap region between sidewalls of the second semiconductor die (70) and sidewalls of the first cavity (36) after mounting the second semiconductor die (70) in the first cavity (36) {Figs. 1, 6; [0040]}.
Regarding claim 21, Oganesian as modified by Aldrete teaches the method of claim 1, but Oganesian does not teach wherein the tip of the copper pillar includes a solder material.
Aldrete teaches in Fig. 2 and paragraph [0005] tip of a copper pillar includes a solder material. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oganesian’s method based as modified by Aldrete on the further teachings of Aldrete, to achieve the above-identified subject matter, so as to form a bond between the copper pillar and another electrical component to which it is attached. Moreover, applying a known technique (e.g., as taught by Aldrete) in the same way to enhance another known technique (e.g., as taught by Oganesian) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C).
Regarding claim 22, Oganesian as modified by Aldrete teaches the method of claim 16, but Oganesian does not teach wherein the tip of the conductive pillar includes a solder material.
Aldrete teaches in Fig. 2 and paragraph [0005] tip of a copper pillar includes a solder material. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oganesian’s method based as modified by Aldrete on the further teachings of Aldrete, to achieve the above-identified subject matter, so as to form a bond between the copper pillar and another electrical component to which it is attached. Moreover, applying a known technique (e.g., as taught by Aldrete) in the same way to enhance another known technique (e.g., as taught by Oganesian) to achieve a predictable result is within the capability of one of ordinary skill in the art. MPEP §2143(I)(C).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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