DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Invention I in the reply filed on 26 February 2026 is acknowledged. Applicants are reminded to indicate a withdrawn status for each of claims 10-15 in their next submission of a claim listing. The restriction is deemed proper and made final.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following subject matter must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 1, line 7, recites an “embedded conductive trace,” which is not illustrated by the drawings and paragraph [0007] of the specification indicates is “not shown.” Each of claims 2, 3, 6, and 16-18 similarly recites the “embedded conductive trace” is objected to for the same reason.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3, lines 2 and 3, recites “the second semiconductor,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution, the claim will be interpreted to recite “the second semiconductor die.”
Claim 18, lines 2 and 3, recites “the second semiconductor,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution, the claim will be interpreted to recite “the second semiconductor die.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-9, and 16-18 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Oganesian et al. (US20180130746A1).
Regarding claim 1, Oganesian teaches in Fig. 1 a method comprising:
forming a first cavity (36) in a backside (side of 26) of a first semiconductor die (20), the first semiconductor die (20) having a back end of line (BEOL) region (region of 30, 32, and/or 24), a front end of line (FEOL) region (region of 38; Figs. 3, 4), and a bulk region (region of 22) {[0029, 0030]}; and
mounting a second semiconductor die (70) in the first cavity (36), a bond pad (84) of the second semiconductor die (70) interconnected through a bottom side (upper portion of 36) of the first cavity (36) with an embedded conductive trace (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {Figs. 1, 3, 4; [0032, 0037, 0038]}.
Regarding claim 2, Oganesian teaches the method of claim 1, and Oganesian further teaches further comprising forming a second cavity (48/50) in the backside (side of 26) of the first semiconductor die (20), the second cavity (48/50) beginning at the bottom side (upper portion of 36) of the first cavity (36), extending vertically through the FEOL region (region of 38), and ending at the embedded conductive trace (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {Figs. 1, 3, 4; [0032]}.
Regarding claim 3, as interpreted in view of the indefiniteness rejection, Oganesian teaches the method of claim 2, and Oganesian further teaches wherein mounting the second semiconductor die (70) in the first cavity (36) further comprises inserting a copper pillar (54) affixed to the bond pad (84) of the second semiconductor die (70) into the second cavity (48/50) to interconnect the bond pad (84) with the embedded conductive trace (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {Figs. 1, 3, 4; [0033]}.
Regarding claim 6, Oganesian teaches the method of claim 1, and Oganesian further teaches wherein mounting the second semiconductor die (70) in the first cavity (36) further comprises applying a compressive force (e.g., gravity/load or bonding) between the second semiconductor die (70) and the first semiconductor die (20) to interconnect the second semiconductor die (70) with the embedded conductive trace (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {[0034, 0042]}.
Regarding claim 7, Oganesian teaches the method of claim 1, and Oganesian further teaches wherein forming the first cavity (36) in the backside (side of 26) of the first semiconductor die (20) includes forming the first cavity (36) by way of a dry etch (e.g., sandblasting) {[0045]}.
Regarding claim 8, Oganesian teaches the method of claim 1, and Oganesian further teaches wherein a backside (side of 76) of the second semiconductor die (70) and the backside (side of 26) of the first semiconductor die (20) are substantially coplanar after mounting the second semiconductor die (70) in the first cavity (36) {Fig. 1; [0009]}.
Regarding claim 9, Oganesian teaches the method of claim 1, and Oganesian further teaches further comprising affixing a plurality of conductive package connectors (34, 60, and/or 62) at an active side (side of 24) of the first semiconductor die (20) {Fig. 1; [0029, 0035]}.
Regarding claim 16, Oganesian teaches in Fig. 1 a method comprising:
forming a first cavity (36) in a backside (side of 26) of a first semiconductor die (20), the first semiconductor die (20) having a back end of line (BEOL) region (region of 30, 32, and/or 24), a front end of line (FEOL) region (region of 38; Figs. 3, 4), and a bulk region (region of 22) {[0029, 0030]}; and
mounting a second semiconductor die (70) in the first cavity (36), the second semiconductor die (70) having a backside (side of 76) and an active side (side of 74), a bond pad (84) at the active side (side of 74) of the second semiconductor die (70) interconnected through a bottom side (upper portion of 36) of the first cavity (36) with an embedded conductive trace (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {Figs. 1, 3, 4; [0032, 0037, 0038]}.
Regarding claim 17, Oganesian teaches the method of claim 16, and Oganesian further teaches further comprising forming a second cavity (48/50) in the backside (side of 26) of the first semiconductor die (20), the second cavity (48/50) beginning at the bottom side (upper portion of 36) of the first cavity (36), extending vertically through the FEOL region (region of 38; Figs. 3, 4), and ending at the embedded conductive trace (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {Figs. 1, 3, 4; [0032]}.
Regarding claim 18, as interpreted in view of the indefiniteness rejection, Oganesian teaches the method of claim 17, and Oganesian further teaches wherein mounting the second semiconductor die (70) in the first cavity (36) further comprises inserting a copper pillar (54) affixed to the bond pad (84) of the second semiconductor die (70) into the second cavity (48/50) to interconnect the bond pad (84) with the embedded conductive trace (52 and/or 58) of the BEOL region (region of 30, 32, and/or 24) of the first semiconductor die (20) {Figs. 1, 3, 4; [0033]}.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Lee (US20240339336A1).
Regarding claim 4, Oganesian teaches the method of claim 1, and Oganesian further teaches further comprising dispensing a thermal compression non-conductive paste (TCNCP) material (44 and/or 86) at the bottom side (upper portion of 36) of the first cavity (36) {[0040, 0042, 0043]}.
Oganesian does not necessarily teach the thermal compression non-conductive paste (TCNCP) material is dispensed before mounting the second semiconductor die in the first cavity. However, Oganesian teaches in Fig. 5 and paragraph [0046] the encapsulant 86 is introduced into the cavities [36] and cured. And the instant application does not identify any new or unexpected result being produced by the specific sequence of operations that is claimed. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oganesian’s method to achieve the above-identified subject matter because the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. MPEP 2144.04(IV)(C).
Regarding claim 5, Oganesian teaches the method of claim 4, and Oganesian further teaches wherein the TCNCP material (44 and/or 86) at least partially fills a gap region between sidewalls of the second semiconductor die (70) and sidewalls of the first cavity (36) after mounting the second semiconductor die (70) in the first cavity (36) {Figs. 1, 6; [0040]}.
Regarding claim 19, Oganesian teaches the method of claim 16, and Oganesian further teaches further comprising dispensing a thermal compression non-conductive paste (TCNCP) material (44 and/or 86) at the bottom side (upper portion of 36) of the first cavity (36) {[0040, 0042, 0043]}.
Oganesian does not necessarily teach the thermal compression non-conductive paste (TCNCP) material is dispensed before mounting the second semiconductor die in the first cavity. However, Oganesian teaches in Fig. 5 and paragraph [0046] the encapsulant 86 is introduced into the cavities [36] and cured. And the instant application does not identify any new or unexpected result being produced by the specific sequence of operations that is claimed. Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Oganesian’s method to achieve the above-identified subject matter because the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. MPEP 2144.04(IV)(C).
Regarding claim 20, Oganesian teaches the method of claim 19, and Oganesian further teaches wherein the TCNCP material (44 and/or 86) at least partially fills a gap region between sidewalls of the second semiconductor die (70) and sidewalls of the first cavity (36) after mounting the second semiconductor die (70) in the first cavity (36) {Figs. 1, 6; [0040]}.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al. (US20180019195A1) teaches a semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die.
Conclusion
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/D.W.W./ Examiner, Art Unit 2891
/MATTHEW C LANDAU/ Supervisory Patent Examiner, Art Unit 2891