DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 5 is objected to because of the following informalities: In claim 5, line 1, a recitation of “a number” should be changed to “the number, for clarity. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 7-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Minoura (US 2013/0075750).
Regarding claim 1, Minoura discloses, as shown in Figures 15A-18, a gallium nitride (GaN) power device comprising:
a substrate (11);
a buffer layer (12);
a GaN channel layer (13); and
a barrier layer (14);
wherein the buffer layer, the GaN channel layer and the barrier layer are stacked sequentially from bottom to top on the substrate;
a p-GaN cap layer (215a) and a p-GaN thin layer (215b) are provided on the barrier layer, and the p-GaN thin layer is configured to cover a surface of the barrier layer and is connected to the p-GaN cap layer; and
an input electrode (22) and an output electrode (23) are also provided on an upper surface of the barrier layer, and a control electrode (21) is provided on an upper surface of the p-GaN cap layer; the control electrode and the p-GaN thin layer are located between the input electrode and the output electrode.
Regarding claim 7, Minoura discloses the p-GaN cap layer and the p-GaN thin layer are configured to deplete the two-dimensional electron gas in the area covered by the p-GaN cap layer and the p-GaN thin layer to make the GaN power device appear in an off state without external bias voltage [0004], [0006], [0090], etc.
Regarding claim 8, Minoura discloses a thickness of the p-GaN thin layer is uniform or changes in a step-like manner (Figures).
Regarding claim 9, Minoura discloses a thickness of the p-GaN thin layer is 5 nm to 150 nm (which is in a range of 1 nm to 400 nm) [0098].
Regarding claim 10, Minoura discloses, as shown in Figures 15A-18, a method for manufacturing a gallium nitride (GaN) power device comprising:
obtaining a basic structure of the GaN power device, wherein the basic structure comprises a substrate (11), a buffer layer (12), a GaN channel layer (13) and a barrier layer (14) stacked in sequence from bottom to top;
depositing a p-GaN epitaxial layer (215) on the barrier layer of the basic structure (Figures 15A-15B);
etching the p-GaN epitaxial layer to form a p-GaN thin layer (215b) and a p-GaN cap layer (215a) connected to the p-GaN thin layer on an upper surface of the barrier layer (Figures 16A-16C); and
providing a control electrode (21) on the p-GaN cap layer, and providing an input (22) electrode and an output electrode (23) on the upper surface of the barrier layer; wherein the control electrode and the p-GaN thin layer are located between the input electrode and the output electrode.
Regarding claim 11, Minoura discloses the etching the p-GaN epitaxial layer to form the p-GaN thin layer and the p-GaN cap layer connected to the p-GaN thin layer on the upper surface of the barrier layer comprises: determining a target number of the p-GaN cap layer and/or state parameters of the p-GaN thin layer according to device design requirements; wherein the state parameters comprise shape and thickness; and etching the p-GaN epitaxial layer according to the target number of the p-GaN cap layer and/or the state parameters of the p-GaN thin layer to form the p-GaN cap layers with the target number and spaced apart from each other on the upper surface of the barrier layer, and/or, to form the p-GaN thin layer corresponding to the state parameters; wherein the p-GaN cap layer near one end of the output electrode is connected to the p-GaN thin layer (Figures 15A-18).
Claim(s) 1-2 and 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (CN 109742142, of record).
Regarding claim 1, Lin et al. discloses, as shown in Figures 1, 3(e), and 4, a gallium nitride (GaN) power device comprising:
a substrate (10);
a buffer layer (20);
a GaN channel layer (30); and
a barrier layer (50);
wherein the buffer layer, the GaN channel layer and the barrier layer are stacked sequentially from bottom to top on the substrate;
a p-GaN cap layer (61) and a p-GaN thin layer (62) are provided on the barrier layer, and the p-GaN thin layer is configured to cover a surface of the barrier layer and is connected to the p-GaN cap layer; and
an input electrode (80) and an output electrode (70) are also provided on an upper surface of the barrier layer, and a control electrode (90) is provided on an upper surface of the p-GaN cap layer; the control electrode and the p-GaN thin layer are located between the input electrode and the output electrode.
Regarding claim 2, Lin et al. discloses the GaN power device is an enhancement mode GaN high electron mobility transistor (HEMT) device; one electrode of a drain electrode and a source electrode of the enhancement mode GaN HEMT device is configured to correspond to the input electrode, and the other electrode of the source electrode and the drain electrode of the enhancement mode GaN HEMT device is configured to correspond to the output electrode; a gate electrode of the enhancement mode GaN HEMT device is configured to correspond to the control electrode (Figures 1 and 3(a)-3(e)).
Regarding claim 7, Lin et al. discloses the p-GaN cap layer and the p-GaN thin layer are configured to deplete the two-dimensional electron gas in the area covered by the p-GaN cap layer and the p-GaN thin layer to make the GaN power device appear in an off state without external bias voltage (Figures 1 and 3(a)-3(e)).
Regarding claim 8, Lin et al. discloses a thickness of the p-GaN thin layer is uniform or changes in a step-like manner (Figures 1 and 3(a)-3(e)).
Regarding claim 9, Lin et al. discloses a thickness of the p-GaN thin layer is 70 nm (which is in a range of 1 nm to 400 nm) (Figure 3(a) and claim 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-6 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Minoura (US 2013/0075750) in view of Shibib et al. (US 2020/0035666).
Regarding claim 2, Minoura discloses the GaN power device is a GaN high electron mobility transistor (HEMT) device. Minoura does not disclose the GaN HEMT is an enhancement mode HEMT device; one electrode of a drain electrode and a source electrode of the enhancement mode GaN HEMT device is configured to correspond to the input electrode (22), and the other electrode of the source electrode and the drain electrode of the enhancement mode GaN HEMT device is configured to correspond to the output electrode (23); a gate electrode of the enhancement mode GaN HEMT device is configured to correspond to the control electrode (21). However, Shibib et al. discloses an enhancement mode HEMT device; one electrode of a drain electrode (220) and a source electrode (225) of the enhancement mode GaN HEMT device is configured to correspond to the input electrode, and the other electrode of the source electrode and the drain electrode of the enhancement mode GaN HEMT device is configured to correspond to the output electrode; a gate electrode (230,235) of the enhancement mode GaN HEMT device is configured to correspond to the control electrode (21). Note Figures 2-3, [0002], [0016], [0019], etc. of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the HEMT of Minoura being an enhancement mode HEMT device, such as taught by Shibib et al. in order to perform the desired function.
Regarding claim 3, Minoura discloses the claimed invention including the power device as explained in the above rejection. Minoura does not disclose the p-GaN thin layer is connected to the drain electrode through a metal electrode, and a Schottky contact is formed between the metal electrode and the p-GaN thin layer. However, Shibib et al. discloses a p-GaN thin layer (235,335) is connected to the drain electrode (220,320) through a metal electrode (270,370), and a Schottky contact is formed between the metal electrode (270,385) and the p-GaN thin layer (370). Note Figures 2-3, [0020], [0025], and [0033] of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Minoura having the p-GaN thin layer is connected to the drain electrode through a metal electrode, and a Schottky contact is formed between the metal electrode and the p-GaN thin layer, such as taught by Shibib et al. in order to further withstand a negative potential between the gate and the source to reduce power loss due to leakage current through the device, without disrupting the operation of the device.
Regarding claim 4, Minoura discloses the claimed invention including the power device as explained in the above rejection. Minoura does not disclose a number of the p-GaN cap layers is multiple, and a gate electrode is provided on each of the p-GaN caps layers correspondingly. However, Shibib et al. discloses a device having a number of cap layers (330,340,355) is multiple, and a gate electrode (330,390) is provided on each of the cap layers correspondingly. Note Figures 2-3 of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Minoura having a number of the cap layers is multiple, and a gate electrode is provided on each of the cap layers correspondingly, such as taught by Shibib et al. in order to further reduce the power loss due to leakage current through the device, without disrupting the operation of the device.
Regarding claim 5, Minoura and Shibib et al. disclose the number of the p-GaN cap layers is two (Figures 2-3).
Regarding claim 6, Minoura discloses the claimed invention including the power device as explained in the above rejection. Minoura does not disclose the GaN power device is a GaN diode, an anode of the GaN diode is configured to correspond to the input electrode, and a cathode of the GaN diode is configured to correspond to the output electrode, and the anode of the GaN diode is electrically connected to the control electrode. However, Shibib et al. discloses a device can be configured to perform the design function as the diode by connecting the input/output electrodes to the control electrode. Note Figures 1-3 of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to connect the input/output electrodes and the control electrode of Minoura to function as the diode, such as taught by Shibib et al. in order to perform the desired function.
Regarding claim 12, Minoura discloses the claimed invention including the method for manufacturing the GaN power device, as explained in the above rejection. Minoura further discloses the providing the control electrode on the p-GaN cap layer, and providing the input electrode and the output electrode on the upper surface of the barrier layer, and the GaN power device is a GaN high electron mobility transistor (HEMT) device. Minoura does not disclose the GaN HEMT is an enhancement mode HEMT device, connecting the p-GaN thin layer to a drain electrode through a metal electrode to form a schottky contact between the metal electrode and the p-GaN thin layer. However, Shibib et al. discloses an enhancement mode HEMT device, connecting a p-GaN thin layer (235,335) to a drain electrode (220,320) through a metal electrode (270,385) to form a schottky contact between the metal electrode and the p-GaN thin layer. Note Figures 2-3, [0002], [0016], [0019], etc. of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the HEMT of Minoura being an enhancement mode HEMT device, such as taught by Shibib et al. in order to perform the desired function.
Regarding claim 13, Minoura discloses the claimed invention including the method for manufacturing the GaN power device, as explained in the above rejection. Minoura further discloses the providing the control electrode on the p-GaN cap layer, and providing the input electrode and the output electrode on the upper surface of the barrier layer. Minoura does not disclose that the GaN power device is a GaN diode by electrically connecting an anode of the GaN diode to the control electrode through an external connection wire. However, Shibib et al. discloses a diode device is formed by connecting the input/output electrode to a control electrode through an external connection wire. Note Figures 1-3 of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to connect the input/output electrodes and the control electrode of Minoura together to function as the diode, such as taught by Shibib et al. in order to perform the desired function.
Claim(s) 3-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (CN 109742142, of record) in view of Shibib et al. (US 2020/0035666).
Regarding claim 3, Lin et al. discloses the claimed invention including the power device as explained in the above rejection. Lin et al. does not disclose the p-GaN thin layer is connected to the drain electrode through a metal electrode, and a Schottky contact is formed between the metal electrode and the p-GaN thin layer. However, Shibib et al. discloses a p-GaN thin layer (235,335) is connected to the drain electrode (220,320) through a metal electrode (270,370), and a Schottky contact is formed between the metal electrode (270,385) and the p-GaN thin layer (370). Note Figures 2-3, [0020], [0025], and [0033] of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Lin et al. having the p-GaN thin layer is connected to the drain electrode through a metal electrode, and a Schottky contact is formed between the metal electrode and the p-GaN thin layer, such as taught by Shibib et al. in order to further withstand a negative potential between the gate and the source to reduce power loss due to leakage current through the device, without disrupting the operation of the device.
Regarding claim 4, Lin et al. discloses the claimed invention including the power device as explained in the above rejection. Lin et al. does not disclose a number of the p-GaN cap layers is multiple, and a gate electrode is provided on each of the p-GaN caps layers correspondingly. However, Shibib et al. discloses a device having a number of cap layers (330,340,355) is multiple, and a gate electrode (330,390) is provided on each of the cap layers correspondingly. Note Figures 2-3 of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the device of Lin et al. having a number of the cap layers is multiple, and a gate electrode is provided on each of the cap layers correspondingly, such as taught by Shibib et al. in order to further reduce the power loss due to leakage current through the device, without disrupting the operation of the device.
Regarding claim 5, Lin et al. and Shibib et al. disclose the number of the p-GaN cap layers is two (Figures 2-3).
Regarding claim 6, Lin et al. discloses the claimed invention including the power device as explained in the above rejection. Minoura does not disclose the GaN power device is a GaN diode, an anode of the GaN diode is configured to correspond to the input electrode, and a cathode of the GaN diode is configured to correspond to the output electrode, and the anode of the GaN diode is electrically connected to the control electrode. However, Shibib et al. discloses a device can be configured to perform the design function as the diode by connecting the input/output electrodes to the control electrode. Note Figures 1-3 of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to connect the input/output electrodes and the control electrode of Minoura to function as the diode, such as taught by Shibib et al. in order to perform the desired function.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (CN 109742142, of record) in view of Minoura (US 2013/0075750).
Regarding claim 10, Minoura discloses, as shown in Figures 1, 3(e), and 4, a method for manufacturing a gallium nitride (GaN) power device comprising:
obtaining a basic structure of the GaN power device, wherein the basic structure comprises a substrate (10), a buffer layer (20), a GaN channel layer (30) and a barrier layer (50) stacked in sequence from bottom to top;
depositing a p-GaN epitaxial layer (60,600) on the barrier layer of the basic structure (Figures 15A-15B);
form a p-GaN thin layer (602) and a p-GaN cap layer (601) connected to the p-GaN thin layer on an upper surface of the barrier layer (Figures 16A-16C); and
providing a control electrode (90) on the p-GaN cap layer, and providing an input (80) electrode and an output electrode (70) on the upper surface of the barrier layer; wherein the control electrode and the p-GaN thin layer are located between the input electrode and the output electrode.
Lin et al. does not disclose etching the p-GaN epitaxial layer to form a p-GaN thin layer (602) and a p-GaN cap layer (601). However, Minoura discloses etching a p-GaN epitaxial layer (215) to form a p-GaN thin layer (215b) and a p-GaN cap layer (215a) connected to the p-GaN thin layer on an upper surface of a barrier layer (14). Note Figures 16A-16C of Minoura. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to etch the p-GaN epitaxial layer of Lin et al. to form a p-GaN thin layer and a p-GaN cap layer, such as taught by Minoura in order to have the desired pattern.
Regarding claim 11, Lin et al. and Minoura disclose the etching the p-GaN epitaxial layer to form the p-GaN thin layer and the p-GaN cap layer connected to the p-GaN thin layer on the upper surface of the barrier layer comprises: determining a target number of the p-GaN cap layer and/or state parameters of the p-GaN thin layer according to device design requirements; wherein the state parameters comprise shape and thickness; and etching the p-GaN epitaxial layer according to the target number of the p-GaN cap layer and/or the state parameters of the p-GaN thin layer to form the p-GaN cap layers with the target number and spaced apart from each other on the upper surface of the barrier layer, and/or, to form the p-GaN thin layer corresponding to the state parameters; wherein the p-GaN cap layer near one end of the output electrode is connected to the p-GaN thin layer (Figures 15A-18).
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (CN 109742142, of record) in view of Minoura (US 2013/0075750) and further in view of Shibib et al. (US 2020/0035666).
Regarding claim 12, Lin et al. and Minoura disclose the claimed invention including the method for manufacturing the GaN power device, as explained in the above rejection. Lin et al. and Minoura further disclose the providing the control electrode on the p-GaN cap layer, and providing the input electrode and the output electrode on the upper surface of the barrier layer, and the GaN power device is a GaN high electron mobility transistor (HEMT) device. Lin et al. and Minoura does not disclose the GaN HEMT is an enhancement mode HEMT device, connecting the p-GaN thin layer to a drain electrode through a metal electrode to form a schottky contact between the metal electrode and the p-GaN thin layer. However, Shibib et al. discloses an enhancement mode HEMT device, connecting a p-GaN thin layer (235,335) to a drain electrode (220,320) through a metal electrode (270,385) to form a schottky contact between the metal electrode and the p-GaN thin layer. Note Figures 2-3, [0002], [0016], [0019], etc. of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the HEMT of Minoura being an enhancement mode HEMT device, such as taught by Shibib et al. in order to perform the desired function.
Regarding claim 13, Minoura discloses the claimed invention including the method for manufacturing the GaN power device, as explained in the above rejection. Minoura further discloses the providing the control electrode on the p-GaN cap layer, and providing the input electrode and the output electrode on the upper surface of the barrier layer. Minoura does not disclose that the GaN power device is a GaN diode by electrically connecting an anode of the GaN diode to the control electrode through an external connection wire. However, Shibib et al. discloses a diode device is formed by connecting the input/output electrode to a control electrode through an external connection wire. Note Figures 1-3 of Shibib et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to connect the input/output electrodes and the control electrode of Minoura together to function as the diode, such as taught by Shibib et al. in order to perform the desired function.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897