DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I: claims 1-12 and 16-20 and Species 3: Fig. 5 in the reply filed on 04/02/2026 is acknowledged. The traversal is on the ground(s) that “claims 13-15 have significant overlapping scope with claims 1-12 and 16-20… see, e.g., claims 1, 2, and 10 compared to 13… which are also included in species 3.” This is found persuasive and therefore, claims 13-15 are reviewed in the examiner’s response below.
Claims 8, 9, 12 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/02/2026.
Claims 1-7,10, 11,13-17 and 20 are examined in the office action correspondence below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/09/2023 is being considered by the examiner.
Drawings
The drawings submitted on 11/09/2023 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 7, 10, 11, 13, 14, 16-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20200350229 A1) in view of Leeyongdeok et al. (KR 100436589 B1).
Regarding claim 1, Chang discloses a semiconductor package comprising:
a substrate (208); (Fig. 8A)
a first semiconductor device (202) on the substrate (208); and
a heat dissipation structure (222+230) on the first semiconductor device (202) including:
a heat dissipation chamber (230) configured to provide an internal space in which a working fluid moves; ([0033]-[0034], Fig. 8A) and
a plurality of first isolation walls (240a/240b/235/237) arranged in the heat dissipation chamber (230) to define a first center channel (236b) and a plurality of first vapor channels (236a/236c) communicating with each other via the first center channel (236b), wherein:
each of the plurality of first isolation walls (240a/240b/235/237) vertically overlaps the first semiconductor device (202), the first center channel (236b) vertically overlaps the first semiconductor device (202), (Fig. 8A)
Chang does not disclose:
and each of the plurality of first vapor channels extends from the first center channel in a lateral direction.
However, Leeyongdeok discloses:
and each of the plurality of first vapor channels (13) extends from the first center channel (13 middle in Fig. 4) in a lateral direction. (Fig. 4 and 5)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang and Leeyongdeok for each of the plurality of first vapor channels extends from the first center channel in a lateral direction so that “vapor from the working fluid by the heat transferred from the heat source can be uniformly moved by the pressure difference.” (Leeyongdeok, Abstract)
Regarding claim 2, Chang discloses the semiconductor package of claim 1, wherein the heat dissipation chamber (230) comprises: a
lower wall (237) attached to the first semiconductor device (202); (Fig. 8A)
an upper wall (235) on the lower wall (237); (Fig. 8A) and
sidewalls (240a/240b) extending between the lower wall (237) and the upper wall (235), and wherein
each of the plurality of first isolation walls (838a/838b) vertically extends from the lower wall (237) of the heat dissipation chamber (230) to the upper wall (235) of the heat dissipation chamber (230). (Fig. 8A)
Regarding claim 3, Chang discloses The semiconductor package of claim 2, wherein each of the plurality of first isolation walls (838a/838b) continuously contacts the lower wall (237), (Fig. 8A/8B)
Chang does not disclose:
And extends from the first center channel to a corresponding sidewall thereto of the sidewalls of the heat dissipation chamber.
However, Leeyongdeok discloses”
And extends from the first center channel (13 middle) to a corresponding sidewall thereto of the sidewalls of the heat dissipation chamber (15). (Fig. 5)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang and Leeyongdeok for the isolation structure to extend from the first center channel to a corresponding sidewall thereto of the sidewalls of the heat dissipation chamber so that “vapor from the working fluid by the heat transferred from the heat source can be uniformly moved by the pressure difference.” (Leeyongdeok, Abstract)
Regarding claim 4, Leeyongdeok discloses the semiconductor package of claim 3, wherein, in a plan view, a horizontal width of each first isolation wall (13) of the plurality of first isolation walls (13) increases toward the sidewall corresponding thereto among the sidewalls of the heat dissipation chamber (15). (Fig. 5)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang and Leeyongdeok for similar reasons mentioned beforehand.
Regarding claim 7, Chang discloses the semiconductor package of claim 5, wherein:
the first semiconductor device (202) comprises a logic chip, (per [0024]) and
the second semiconductor device (204a) comprises a memory chip. (per [0024])
Regarding claim 10, Chang discloses the semiconductor package of claim 1, wherein the heat dissipation structure (222+2330) further comprises a plurality of micro-protruding structures arranged (indirectly) on an external surface of the heat dissipation chamber (230). (Fig. 8A)
Regarding claim 11, Chang discloses the semiconductor package of claim 1, further comprising a first wick structure (232) provided on an internal surface of the heat dissipation chamber (230) and configured to guide a working fluid in a liquid phase. (per [0034], Fig. 8A)
Regarding claim 13, Chang discloses a semiconductor package comprising:
a package substrate (208); (Fig. 8A)
an interposer substrate (206) on the package substrate (208); (Fig. 8A)
a plurality of semiconductor devices (202, 204a, 204b) mounted on the interposer substrate (206) and apart from each other; (Fig. 8A) and
a heat dissipation structure (222+230) arranged on the plurality of semiconductor devices (202, 204a, 204b), wherein the heat dissipation structure (222+230) comprises: a heat dissipation chamber (230) including a lower wall (237), an upper wall (235), and sidewalls (240a/240b), and configured to provide an internal space in which a working fluid moves; ([0033]-[0034], Fig. 8A)
a plurality of first isolation walls (828a/838b) arranged in the heat dissipation chamber (230) to form a first center channel (236b) and a plurality of first vapor channels (236a/236c) communicating with each other via the first center channel (236b) and extending radially from the first center channel(236b); (Fig. 8A) and
a plurality of micro-protruding structures (on 222) arranged on an external surface of the heat dissipation chamber (230), wherein the first center channel (236b) vertically overlaps a first semiconductor device (202) of the plurality of semiconductor devices (202, 204a, 204b)
Chang does not disclose:
and wherein each of the plurality of first isolation walls continuously extends horizontally from a first end thereof on the first semiconductor device to a second end thereof connected to any one of the sidewalls of the heat dissipation chamber.
However, Leeyongdeok discloses:
wherein each of the plurality of first isolation walls (13) continuously extends horizontally from a first end thereof on the first semiconductor device (1) to a second end thereof connected to any one of the sidewalls of the heat dissipation chamber (15). (Fig. 5)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang and Leeyongdeok for each of the plurality of first isolation walls continuously extends horizontally from a first end thereof on the first semiconductor device to a second end thereof connected to any one of the sidewalls of the heat dissipation chamber so that “vapor from the working fluid by the heat transferred from the heat source can be uniformly moved by the pressure difference.” (Leeyongdeok, Abstract)
Regarding claim 14, Chang discloses the semiconductor package of claim 13, wherein each of the plurality of first isolation walls (838a/838b) extends from the lower wall (237) to the upper wall (235) of the heat dissipation chamber (230), and contacts the lower wall (237) and the upper wall (235) of the heat dissipation chamber (230) throughout its horizontal length. (Fig. 8A)
Regarding claim 16, Chang discloses a heat dissipation structure comprising:
a heat dissipation chamber (230) including a lower wall (237) in contact with a heat source (202, 204a, 204b), an upper wall (235) on the lower wall (237), and sidewalls extending between the lower wall (237) and the upper wall (235), and configured to provide an internal space in which a working fluid moves; ([0033]-[0034], Fig. 8A) and
a plurality of first isolation walls (838a/838b) extending horizontally and arranged in the heat dissipation chamber (230) to form a first center channel (236b) and a plurality of first vapor channels (236a/236c) communicating with each other via the first center channel (236b), (Fig. 8A)
Chang does not disclose:
wherein the plurality of first vapor channels radially extend from the first center channel.
However, Leeyongdeok discloses:
the plurality of first vapor channels (13) radially extend from the first center channel (middle 13 in Fig. 4). (Fig. 4 and 5)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang and Leeyongdeok for the plurality of first vapor channels radially extend from the first center channel so that “vapor from the working fluid by the heat transferred from the heat source can be uniformly moved by the pressure difference.” (Leeyongdeok, Abstract)
Regarding claim 17, Chang discloses the heat dissipation structure of claim 16, wherein each of the plurality of first isolation walls (838a/838b) extends from the lower wall (237) to the upper wall (235) of the heat dissipation chamber (230), contacts the lower wall (237) and the upper wall (235) of the heat dissipation chamber (230) throughout its horizontal length, (Fig. 8A/8B)
Chang Fig. 8A/8B do not disclose:
and is connected to any one of sidewalls of the heat dissipation chamber.
However, Chang Fig. 6 and/or 7 disclose:
is connected to any one of sidewalls (239a/239b) of the heat dissipation chamber (230). (Fig. 2A)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang Fig. 8A/8B and Figs. 6 and 7 for the plurality of first isolation walls…is connected to any one of sidewalls of the heat dissipation chamber in order to “ the vapor chamber is modified to limit or otherwise inhibit thermal crosstalk.” (Chang, [0014])
Regarding claim 18, Leeyongdeok discloses the heat dissipation structure of claim 17, wherein, in a plan view, a width of each first isolation wall (13) of the plurality of first isolation walls (13) increases toward a corresponding sidewall thereto of the sidewalls of the heat dissipation chamber (15). (Fig. 5)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang and Leeyongdeok for similar reasons mentioned beforehand.
Regarding claim 20, Chang discloses the heat dissipation structure of claim 16, further comprising a plurality of micro- protruding structures (on 222) arranged (indirectly) on an external surface of the heat dissipation chamber (230). (Fig. 8A)
Claims 5, 6, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 20200350229 A1), as applied to claims 1 and 14 above, and further in view of McNamara et al. (US 20200161215 A1).
Regarding claim 5, Chang discloses the semiconductor package of claim 1, further comprising a second semiconductor device (204a) arranged on the substrate (208), wherein:
the heat dissipation structure (222+230) covers the second semiconductor device (204a), consumed power of the first semiconductor device (202) is greater than consumed power of the second semiconductor device (204a),
Chang does not disclose:
and at least one of the plurality of first isolation walls vertically overlaps both the first semiconductor device and the second semiconductor device.
However, McNamara discloses:
and at least one of the plurality of first isolation walls (235a-235f) vertically overlaps both the first semiconductor device (117) and the second semiconductor device (217). (Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang and McNamara for at least one of the plurality of first isolation walls vertically overlaps both the first semiconductor device and the second semiconductor device in order to “provide for an integrated heat spreader that has configurable heat fins so that a common shell design can provide thermal management for a variety of different chip and circuit board combinations and heat flux values.” (McNamara, [0021])
Regarding claim 6, McNamara discloses the semiconductor package of claim 5, wherein, in a plan view, at least one of the plurality of first isolation walls (235f-235g) extends across the second semiconductor device (217). ([0053], Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang and McNamara for similar reasons mentioned beforehand.
Regarding claim 15, Chang discloses the semiconductor package of claim 14, wherein the plurality of semiconductor devices (202, 204a, 204b) comprise a second semiconductor device (204a) apart from the first semiconductor device (202), (Fig. 8A)
wherein the first semiconductor device (202) comprises a logic chip (per [0024]), and the second semiconductor device (204a) comprises a memory chip (per [0024]),
Chang does not disclose:
wherein, in a plan view, at least one of the plurality of first isolation walls extends across the second semiconductor device.
However, McNamara discloses:
in a plan view, at least one of the plurality of first isolation walls (235f-235g) extends across the second semiconductor device (217). (Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Chang and McNamara for in a plan view, at least one of the plurality of first isolation walls extends across the second semiconductor device in order to “provide for an integrated heat spreader that has configurable heat fins so that a common shell design can provide thermal management for a variety of different chip and circuit board combinations and heat flux values.” (McNamara, [0021])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ASHLEY NICOLE BLACKWELL/
Examiner
Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights