DETAILED ACTION
This Office action is in response to the election filed 29 April 2026. Claims 1-16 are currently pending; claims 8-16 have been withdrawn by Applicant.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-7, in the reply filed on 29 April 2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "corresponding to a position of the connecting board with each other" in the last line. It is unclear what structural relationship with the solder ball or to what element this limitations refers. For the purposes of examination, it is assumed the solder ball is disposed outside the molding layer and on the connecting board.
Claims 2-7 depend directly or indirectly from claim 1 and thus also contain the above indefinite language.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0228746 A1 to Nagata (hereinafter “Nagata”) in view of US 2012/0112329 A1 to Yen et al. (hereinafter “Yen”) and US 2021/0013256 A1 to Lin et al. (hereinafter “Lin”).
Regarding independent claim 1, as best understood, Nagata (Fig. 1) discloses a microminiature image acquisition and processing system package structure, comprising:
optical glass 14 (¶ 0027), a cofferdam 34 (¶ 0029) being formed around a second surface (bottom) of the optical glass 14 (Fig. 1);
a CMOS chip 31 (¶¶ 0029, 71), a first surface (top) of the CMOS chip being provided with a photosensitive 21 (¶ 0028) and microlens region 22 (¶ 0028) and a metal bonding pad 32 (¶ 0031), a through-silicon via 35 (¶ 0034) is etched in a second surface (bottom) of the CMOS chip 31 until it extends to the metal bonding pad 32 on the first surface (top) of the CMOS chip, the cofferdam 34 being seamlessly connected to the metal bonding pad 32 and an edge region around the CMOS chip through an adhesive film 33 (¶ 0032) and covering the first surface (top) of the CMOS chip 31 to form a cavity (21/22 disposed therein), the photosensitive 21 and microlens region 22 being located in the cavity (Fig. 1);
a wafer Re-Distribution Layer (including 36/37/38, ¶ 0034), a first layer 36 of the wafer Re-Distribution Layer covering the second surface (bottom) of the CMOS chip 31 and extending to a through-silicon via region 35 (Fig. 1); and
a molding layer 39 (¶ 0035), the molding layer being configured to perform encapsulating on the second surface (bottom) of the CMOS chip 31 (39 covers the second surface of 31), a solder ball 40 (¶ 0035) being disposed outside the molding layer 39.
Nagata fails to expressly disclose optical coated glass being provided with a protective film. In the same field of endeavor, Yen (Fig. 1) discloses a package structure including a first surface (top) of optical coated glass 114 (¶ 0034) being provided with a protective film (¶ 0034 - filters and/or anti-reflective layers formed on 114). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the optical coated glass with protective film as taught by Yen in the package of Nagata for the purpose of providing a glass with superior optical qualities for improving sensitivity of the photosensitive device.
Nagata and Yen fail to expressly disclose: an image processor and coder, a master controller, a Flash, a power supply and a connecting board being disposed on an outermost layer of the wafer Re-Distribution Layer; the solder ball corresponding to a position of the connecting board with each other. In the same field of endeavor, Lin (Fig. 5) discloses a package structure including an image sensor chip 12 (¶ 0023) and wafer Re-Distribution layer 16 (¶ 0023), wherein additional chips 14/54 (¶ 0034 - memory, logic, functional chips) and a connecting board 60 (¶ 0044) being disposed on an outermost layer 16 of the wafer Re-Distribution Layer 16; a solder ball 52 (¶ 0033) corresponding to a position of the connecting board 60 (Fig. 5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package structure of Nagata and Yen with the teachings of Lin to include an image processor and coder, a master controller, a Flash, a power supply, and a connecting board in the manner recited, for the purpose of providing faster communication and operation between components since connection wiring is shorter when within the same package (Lin, ¶¶ 0004-05).
Regarding claim 6, Nagata, Yen, and Lin disclose the microminiature image acquisition and processing system package structure according to claim 1, Lin (Fig. 5) discloses further wherein the connecting board 60 is higher than the image processor and coder, the master controller, the Flash, and the power supply, respectively (Lin, Fig. 5 - H1 of 60 is higher than T1 of 14 or height of 54; ¶ 0044).
Claims 2-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Nagata, Yen, and Lin as applied to claim 1 above, and further in view of US 2018/0012863 A1 to Yu et al. (hereinafter “Yu”).
Regarding claim 2, Nagata, Yen, and Lin disclose the microminiature image acquisition and processing system package structure according to claim 1, however fail to expressly disclose: wherein the wafer Re-Distribution Layer comprises passivation layers and metal layers, which are bonded to each other; a number of the passivation layers is greater than that of the metal layers by one layer; and the first layer of the wafer Re-Distribution Layer is one passivation layer of the passivation layers, and the outermost layer of the wafer Re-Distribution Layer is another passivation layer of the passivation layers.
In the same field of endeavor, Yu (Fig. 2B) discloses a package structure including a wafer Re-Distribution Layer 170 (¶ 0018) comprises passivation layers and metal layers, which are bonded to each other (¶ 0018 - “more than one polymer dielectric material layers and more than one metallization layers in alternation”); a number of the passivation layers is greater than that of the metal layers by one layer (¶ 0018 - “metallization layers may be sandwiched between the polymer dielectric material layers”); and the first layer of the wafer Re-Distribution Layer is one passivation layer of the passivation layers, and the outermost layer of the wafer Re-Distribution Layer is another passivation layer of the passivation layers (the “wafer Re-Distribution Layer” may be defined to include passivation layers as the “first layer” and “outermost layer” such that this limitation is met). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a wafer Re-Distribution Layer as taught by Yu in the package structure of Nagata, Yen, and Lin for the purpose of providing an art-recognized and conventional configuration of a redistribution layer providing electrical connection between the package contents and external components.
Regarding claim 3, Nagata, Yen, Lin, and Yu disclose the microminiature image acquisition and processing system package structure according to claim 2, wherein the metal layers comprises a first metal layer 37 (Nagata, Fig. 1) and a second metal layer (Yu, Fig. 2B - comprised in 170); and the passivation layers comprises a first passivation layer 36 (Nagata, Fig. 1), a second passivation layer and a third passivation layer (Yu, Fig. 2B - comprised in 170); and the first passivation layer 36 (Nagata, Fig. 1) covers the second surface (bottom) of the CMOS chip 31 (Nagata, Fig. 1) and extends to the through-silicon via region 35 (Nagata, Fig. 1), the first metal layer 37 covers the first passivation layer 36 and extends into the through-silicon via 35 so that the first surface (top) and the second surface (bottom) of the CMOS chip are electrically connected (Nagata, Fig. 1 - 37 in electrical connection with 32 on first surface through 34), and the second passivation layer, the second metal layer and the third passivation layer sequentially cover the first metal layer (Yu, Fig. 2B - 170 comprising the second passivation layer, the second metal layer and the third passivation layer).
Regarding claim 4, Nagata, Yen, Lin, and Yu disclose the microminiature image acquisition and processing system package structure according to claim 2, however fail to expressly disclose: wherein a number of the metal layers is three or more, and a number of the passivation layers is four or more. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide additional metal layers and passivation layers to arrive at the above recited amount, since the courts have held that mere duplication of parts has no patentable significance unless a new or unexpected result is produced see In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). Here, the instant specification and record is silent as to a new or unexpected result produced by the recited number of metal layers and passivation layers, thus the duplication of said metal layers and passivation layers is deemed to have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 7, Nagata, Yen, Lin, and Yu disclose the microminiature image acquisition and processing system package structure according to claim 2, wherein the image processor and coder, the master controller, the Flash, and the power supply are designed by means of flip chip (Lin, Fig. 5 - 14, 54 are flip chips) or wire bonding and stacking, and are communicated through the metal layers 16 (Lin, Fig. 5) or by means of metal wire bonding.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nagata, Yen, and Lin as applied to claim 1 above, and further in view of US 2016/0307941 A1 to Cheng et al. (hereinafter “Cheng”).
Regarding claim 5, Nagata, Yen, and Lin disclose the microminiature image acquisition and processing system package structure according to claim 1, wherein the protective film is an anti-reflective coating (Yen, ¶ 0034), however fail to expressly disclose: the protective film is made of a metal, a polymer or a mixture of the metal and the polymer. In the same field of endeavor, Cheng discloses anti-reflective coatings can be made of a polymer (¶ 0016). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the material of Cheng in the protective film of the system package of Nagata, Yen, and Lin since polymer is a material known in the art to be suitable for use in anti-reflective coatings, as exemplified by Cheng at ¶ 0016.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2019/0348459 A1 to Katkar disclosing an image sensor package structure.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
27 June 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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