DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election with traverse of the Restriction Requirement in the reply filed on 18 February 2026 is acknowledged. The traversal is on the ground(s) that that there would be no undue burden on the Examiner to additionally examine claims 17-20 of Group II along with the claims of Group I. This is not found persuasive for the reasons identified in the Restriction Requirement dated 8 January 2026.
The requirement is still deemed proper and is therefore made FINAL. Applicants are reminded to indicate the status of the withdrawn claims 17-20 in their next submission of a claim listing.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 6, and 7 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chen et al. (US20230062454A1).
Regarding claim 1, Chen teaches in Fig. 2C a chip package comprising:
one or more integrated circuit IC dies (132) {[0017]};
a package substrate (100) having a first surface (102), the first surface (102) having a first region (region directly below 132) and a second region (region directly below 200) disposed outward of the first region (region directly below 132), the first region (region directly below 132) configured to be covered by the one or more IC dies (132), at least one of the one or more integrated circuit IC dies (132) mounted to the first surface (102) {[0016, 0017]};
a raised surface (200/230/232) formed on the second region (region directly below 200) of the first surface (102) of the package substrate (100) {[0019]}; and
a package lid (330) mounted to the raised surface (200/230/232) {[0020]}.
Regarding claim 3, Chen teaches the chip package of claim 1, and Chen further teaches further comprising an adhesive material (230) fixing the lid (330) to the raised surface (200) {Fig. 2C; [0019]}.
Regarding claim 6, Chen teaches the chip package of claim 1, and Chen further teaches wherein the raised surface (230/232) is comprised of one or more dielectric layers disposed on the first surface (102) of the package substrate (100) {Fig. 2C; [0019], 230, 232 may be made of epoxy, urethane, or polyurethane, which are each a dielectric}.
Regarding claim 7, Chen teaches the chip package of claim 1, and Chen further teaches further comprising:
one or more surface mounted components (120) mounted to the first surface (102) of the package substrate (100) inward of the raised surface (200/230/232) {Fig. 2C; [0016]}.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Lee (US20240339336A1).
Regarding claim 2, Chen teaches the chip package of claim 1, but Chen does not teach wherein the raised surface has a height between 30 and 50 micrometers above the first surface of the package substrate.
In an analogous art, Lee teaches in Fig. 5 and paragraph [0060] a raised surface (110; solder resist) has a height of 10 micrometers or more above a first surface (upper surface) of a package substrate (100). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s chip package based on the teachings of Lee, to achieve the above-identified subject matter – so as to reduce the flow of solder into the region occupied by the raised surface. Moreover, all the claimed elements (e.g., raised surface, substrate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Lee) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 4, Chen teaches the chip package of claim 1, but Chen does not teach wherein the raised surface is comprised of a solder resist disposed on the first surface of the package substrate.
Lee teaches in Fig. 5 and paragraph [0060] a raised surface (110) is comprised of a solder resist disposed on a first surface (upper surface) of a package substrate (100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s chip package based on the teachings of Lee, to achieve the above-identified subject matter – so as to reduce the flow of solder into the region occupied by the raised surface. Moreover, all the claimed elements (e.g., solder resist, raised surface, substrate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Lee) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Huang et al. (US20240363547A1).
Regarding claim 5, Chen teaches the chip package of claim 1, but Chen does not teach wherein the raised surface is comprised of one or more layers of polymer materials disposed on the first surface of the package substrate.
However, Chen teaches in paragraph [0019] the raised surface (230/232) may include epoxy or silicone.
In an analogous art, Huang teaches in Fig. 1D and paragraphs [0082, 0086] a raised surface (170, 180, and/or 190) is comprised of one or more layers of polymer materials (e.g., epoxy or silicone) disposed on a first surface of a package substrate (110). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s chip package based on the teachings of Huang, to achieve the above-identified subject matter – so as to bond the raised surface and the lid. Chen [0019]. Moreover, all the claimed elements (e.g., raised surface, substrate, polymer material) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Huang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding claim 8, Chen teaches the chip package of claim 7, but Chen does not teach further comprising:
a third region free from and outward of the one or more surface mounted components, wherein the third region spans a distance of 0.5 millimeters to 1.5 millimeters from the raised surface to the one or more surface mounted components.
However, Chen teaches in Fig. 2C and paragraph [0016] a third region (region between 120 and 200/230/232) free from and outward of the one or more surface mounted components (120), wherein the third region (region between 120 and 200/230/232) spans a distance from the raised surface (200/230/232) to the one or more surface mounted components (120). Regarding the recited distance being 0.5 millimeters to 1.5 millimeters, the instant application does not identify any criticality, unexpected outcome, or difference in functionality/operation arising from the recited range. [Where] the dimensional limitations [of the claimed device] d[o] not specify a device which perform[s] and operate[s] any differently from the prior art, a difference between such claimed dimensional limitations and those existing in the prior art is insufficient to render the claimed device non-obvious over the prior art. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 1345, 1349 (Fed. Cir. 1984).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claim 1 above, and further in view of Hung et al. (US20210343619A1).
Regarding claim 9, Chen teaches the chip package of claim 1, but Chen does not teach wherein the raised surface is discontinuous and segmented into discrete elements.
In an analogous art, Hung teaches in Figs. 3 and 11 and paragraphs [0026, 0041] a raised surface (122) is discontinuous and segmented into discrete elements. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s chip package based on the teachings of Hung, to achieve the above-identified subject matter – because all the claimed elements (e.g., raised surface, discrete elements) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hung) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 10, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lim (US8598698B1) and Toong et al. (US20100181644A1).
Regarding claim 10, Chen teaches in Fig. 2C a chip package comprising:
a first integrated circuit (IC) die (132) {[0017]};
a package substrate (100) having a first surface (102), the first surface (102) having a first region (region directly below 132) and a second region (region directly below 200) disposed outward of the first region (region directly below 132), the first IC die (132) mounted to the first region (region directly below 132) {[0016, 0017]};
a plurality of passive devices (120) mounted to the first surface (102) of the package substrate (100) between the first (region directly below 132) and second (region directly below 200) regions {[0016]};
one or more raised surfaces (200/230/232) disposed on the second region (region directly below 200) of the first surface (102) of the package substrate (100) {[0019]}; and
a package lid (330) affixed to the one or more raised surfaces (200/230/232) {[0020]}.
Chen does not expressly teach the plurality of passive devices are chip capacitors.
In an analogous art, Lim teaches in lines 32-34 of column 1 that chip capacitors are passive devices. In another analogous art, Toong teaches in Fig. 1 and paragraph [0023] a plurality of chip capacitors (130) mounted to a first surface (upper surface) of a package substrate (108) between a first region (region directly below 102) and a second region (region directly below 123). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s chip package based on the teachings of Lim and Toong, to achieve the above-identified subject matter – to remove unwanted signals or reduce power supply noise to the chip. Toong [0002]. Moreover, all the claimed elements (e.g., chip capacitors, first and second regions of a substrate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Toong) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 15, Chen as modified by Lim and Toong teaches the chip package of claim 10, and Chen further teaches wherein the raised surfaces (230/232) are comprised of one or more dielectric layers disposed on the first surface (102) of the package substrate (100) {Fig. 2C; [0019], 230, 232 may be made of epoxy, urethane, or polyurethane, which are each a dielectric}.
Regarding claim 16, Chen as modified by Lim and Toong teaches the chip package of claim 10, but Chen does not teach further comprising:
a free region and outward of the plurality of chip capacitors, wherein the free region spans a distance of 0.5 millimeters to 1.5 millimeters from the raised surfaces to the plurality of chip capacitors.
However, Chen teaches in Fig. 2C and paragraph [0016] a free region (region between 120 and 200/230/232) and outward of the plurality of chip capacitors (modified 130), wherein the free region (region between 120 and 200/230/232) spans a distance from the raised surfaces (200/230/232) to the plurality of chip capacitors (modified 130). Regarding the recited distance being 0.5 millimeters to 1.5 millimeters, the instant application does not identify any criticality, unexpected outcome, or difference in functionality/operation arising from the recited range. [Where] the dimensional limitations [of the claimed device] d[o] not specify a device which perform[s] and operate[s] any differently from the prior art, a difference between such claimed dimensional limitations and those existing in the prior art is insufficient to render the claimed device non-obvious over the prior art. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 1345, 1349 (Fed. Cir. 1984).
Claim(s) 11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lim and Toong as applied to claim 10 above, and further in view of Lee.
Regarding claim 11, Chen as modified by Lim and Toong teaches the chip package of claim 10, but Chen does not teach wherein the raised surfaces have a height between 30 and 50 micrometers above the first surface of the package substrate.
Lee teaches in Fig. 5 and paragraph [0060] raised surfaces (110; of solder resist) have a height of 10 micrometers or more above a first surface (upper surface) of a package substrate (100). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s chip package as modified by Lim and Toong based on the teachings of Lee, to achieve the above-identified subject matter – so as to reduce the flow of solder into the region occupied by the raised surface. Moreover, all the claimed elements (e.g., raised surface, substrate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Lee) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Regarding claim 13, Chen as modified by Lim and Toong teaches the chip package of claim 10, but Chen does not teach wherein the raised surfaces are comprised of a solder resist disposed on the first surface of the package substrate.
Lee teaches in Fig. 5 and paragraph [0060] raised surfaces (110) are comprised of a solder resist disposed on a first surface (upper surface) of a package substrate (100). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s chip package as modified by Lim and Toong based on the teachings of Lee, to achieve the above-identified subject matter – so as to reduce the flow of solder into the region occupied by the raised surface. Moreover, all the claimed elements (e.g., solder resist, raised surfaces, substrate) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Lee) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lim and Toong as applied to claim 10 above, and further in view of Hung.
Regarding claim 12, Chen as modified by Lim and Toong teaches the chip package of claim 10, but Chen does not teach wherein the raised surfaces are discontinuous and segmented into discrete elements.
Hung teaches in Figs. 3 and 11 and paragraphs [0026, 0041] raised surfaces (122) are discontinuous and segmented into discrete elements. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s chip package as modified by Lim and Toong based on the teachings of Hung, to achieve the above-identified subject matter – because all the claimed elements (e.g., raised surfaces, discrete elements) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Hung) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Moreover, [t]he selection of a known … [structure] based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Lim and Toong as applied to claim 10 above, and further in view of Huang.
Regarding claim 14, Chen as modified by Lim and Toong teaches the chip package of claim 10, but Chen does not teach wherein the raised surfaces are comprised of one or more layers of polymer materials disposed on the first surface of the package substrate.
However, Chen teaches in paragraph [0019] the raised surfaces (230/232) may include epoxy or silicone.
Huang teaches in Fig. 1D and paragraphs [0082, 0086] raised surfaces (170, 180, and/or 190) are comprised of one or more layers of polymer materials (e.g., epoxy or silicone) disposed on a first surface of a package substrate (110). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Chen’s chip package as modified by Lim and Toong based on the teachings of Huang, to achieve the above-identified subject matter – so as to bond the raised surface and the lid. Chen [0019]. Moreover, all the claimed elements (e.g., raised surfaces, substrate, polymer material) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Huang) with no change in their respective functions, and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A). Furthermore, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zohni et al. (US10840192B1) teaches a chip package assembly and method for fabricating the same are provided which utilize a stiffener to improve a package substrate against out of plane deformation. In one example, a chip package assembly is provided that includes a package substrate, at least one integrated circuit (IC) die and a stiffener. The package substrate has a first surface and a second surface coupled by a side wall. The at least one IC die is disposed on the first surface of the package substrate. The stiffener is disposed outward of the at least one IC die. The stiffener has a first surface disposed outward of and bonded to the side wall of the package substrate. The stiffener has a second surface bonded to at least one of the first and second surfaces of the package substrate.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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