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DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements filed 12/08/2023 and 05/28/2024 have been fully considered and is attached hereto.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the heat conductive material covers at least one portion of the at least one patterned heat dissipation structure and covers at least one portion of the circuit” in Claim 8, and “wherein the heat conductive material is located between the circuit and the top surface” in Claim 9 must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended”. If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 10-11 and 16 are rejected under 35 U.S.C. § 103 as being unpatentable over Syu et al (2018/0082936) in view of Otsubo et al (US 2021/0366839).
Regarding Claim 1, Syu (In Fig 1E) discloses a molded electronic assembly (10a), comprising:
a circuit substrate (201/202/203/205), comprising a substrate (202) and a circuit (201/203/205), wherein the substrate (202) has a top surface (Fig 1E), the circuit (201/203/205) has a plurality of signal contacts (205), and the signal contacts are distributed on the top surface (Fig 1E);
a plurality of electronic devices (300), disposed on the circuit substrate (201/202/203/205), each of the electronic devices (300) having a plurality of device pins (310) connected to the signal contacts (205); and
at least one patterned heat dissipation structure (204), (¶ 38, II. 30-33), corresponding to a signal contact (205) of the signal contacts (205) and starting from the corresponding signal contact (205) and extending toward a plurality of directions on the top surface of the substrate (202), (Fig 1E), however Syu does not disclose wherein a plurality of electronic devices disposed on the circuit substrate.
Instead, Otsubo (In Fig 1) teaches wherein a plurality of electronic devices (31/3a/3b) disposed on the circuit substrate (1), (Fig 1).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Morse Otsubo with a plurality of electronic devices disposed on the circuit substrate to benefit from providing a module capable of enhancing the heat dissipation from various components mounted on top surface of the substrate (Otsubo, ¶ 8, II. 1-3).
Examiner Note; it should be mentioned that; the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. See: St. Regis Paper Co. v. Bernis Co., 193: USPQ 8, see: MPEP 214404 section VI.
Regarding Claim 2, Syu in view of Otsubo discloses the limitations of Claim 1, however Syu (In Fig 1E) further discloses wherein the molded electronic assembly (10a) further comprising a first cover layer (420a) disposed on the substrate (202) and covering the at least one patterned heat dissipation structure (204) and at least parts of the electronic devices (300), (Fig 1E).
Regarding Claim 4, Syu in view of Otsubo discloses the limitations of Claim 2, however Syu as modified does not disclose wherein the molded electronic assembly further comprising a second cover layer, wherein the first cover layer is located between the second cover layer and the substrate, and the second cover layer covers the electronic devices.
Instead, Otsubo (In Fig 1) further teaches wherein the molded electronic assembly (101) further comprising a second cover layer (5), wherein the first cover layer (6a) is located between the second cover layer (5) and the substrate (1), and the second cover layer (5) covers the electronic devices (31/3a/3b), (Fig 1).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Morse Otsubo with a second cover layer, and the first cover layer being located between the second cover layer and the substrate, and the second cover layer covers the electronic devices to benefit from providing a module capable of enhancing the heat dissipation from various components mounted on top surface of the substrate (Otsubo, ¶ 8, II. 1-3).
Regarding Claim 10, Syu in view of Otsubo discloses the limitations of Claim 2, however Syu as modified does not disclose wherein the substrate has a plurality of grooves recessed from the top surface, and the signal contacts are disposed in the grooves.
Instead, Otsubo (In Fig 1) wherein the substrate (1) has a plurality of grooves (grooves accommodating 12), (Fig 1) recessed from the top surface (top surface of 1), and the signal contacts (12) are disposed in the grooves (grooves accommodating 12), (Fig 1).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo with the substrate having a plurality of grooves recessed from the top surface, and the signal contacts are disposed in the grooves to benefit from providing a module capable of enhancing the heat dissipation from various components mounted on top surface of the substrate (Otsubo, ¶ 8, II. 1-3).
Regarding Claim 11, Syu in view of Otsubo discloses the limitations of Claim 1, however Syu (In Fig 1E) further discloses wherein the at least one patterned heat dissipation structure (204) has a heat input terminal (input portion of 204 attached to 31) and a plurality of heat output terminals (output portion 204 furthest away from 31), (Fig 1E), the heat input terminal (input portion of 204 attached to 31) contacts a corresponding device pin (310) of the device pins (31) or a corresponding signal contact (205) of the signal contacts (205), (Fig 1E), and the heat output terminals (output portion 204 furthest away from 31) extend toward different directions from the heat input terminal (input portion of 204 attached to 31), (Fig 1E).
Regarding Claim 16, Syu in view of Otsubo discloses the limitations of Claim 1, however Syu (In Fig 1E) further discloses wherein the number of the at least one patterned heat dissipation structure (204) is plural (Fig1E), and each of the patterned heat dissipation structures (204) starts from the corresponding signal contact (205) and extends toward a plurality of directions on the top surface of the substrate (202), (Fig 1E).
Claim 3 is rejected under 35 U.S.C. § 103 as being unpatentable over Syu in view of Otsubo and further in view of Lai et al (TW201025523).
Regarding Claim 3, Syu in view of Otsubo discloses the limitations of Claim 2, however Syu as modified does not disclose wherein a height of the first cover layer is lower than or equal to a height of the electronic devices.
Instead, Lai (In Fig H) teaches wherein a height of the first cover layer (39) is lower than or equal to a height of the electronic devices (34), (Fig H).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo and further with Lai with a height of the first cover layer being lower than or equal to a height of the electronic devices to benefit from protecting the electrical contacts and preventing contamination (Lai, ¶ 3, I. 4).
Claim 5 is rejected under 35 U.S.C. § 103 as being unpatentable over Syu in view of Otsubo and further in view of Lai and further in view of Vepakomma (US 2022/0093480).
Regarding Claim 5, Syu in view of Otsubo and further in view of Lai discloses the limitations of Claim 4, however Syu as modified does not disclose wherein a Young's coefficient of the second cover layer is greater than a Young's coefficient of the first cover layer, and a heat conductive coefficient of the second cover layer is less than a heat conductive coefficient of the first cover layer.
Instead, Vepakomma (In Fig 2) teaches wherein a Young's coefficient of the second cover layer (214) is greater than a Young's coefficient of the first cover layer (212), (¶ 19, II. 1-13), and a heat conductive coefficient of the second cover layer (214), (resin, ¶ 23, II. 3-5) is less than a heat conductive coefficient of the first cover layer (212), (KER-6020-F, ¶ 22, 9-13).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo further with Lai and further with Vepakomma with a Young's coefficient of the second cover layer being greater than a Young's coefficient of the first cover layer, and a heat conductive coefficient of the second cover layer being less than a heat conductive coefficient of the first cover layer to benefit from reducing stress which may cause cracks in solder joints due to constant thermal cycles affect solder joint reliability (Vepakomma, ¶ 2, II. 9-12, ¶ 3, II. 6-14).
Claims 6-9 are rejected under 35 U.S.C. § 103 as being unpatentable over Syu in view of Otsubo and further in view of Wang et al (US 12,245,358).
Regarding Claim 6, Syu in view of Otsubo discloses the limitations of Claim 1, however Syu as modified does not disclose wherein the molded electronic assembly further comprising a heat conductive material disposed on the substrate and surrounding the device pins.
Instead, Wang (In Fig 13) teaches wherein the molded electronic assembly (100) further comprising a heat conductive material (23) disposed on the substrate (22) and surrounding the device pins (201), (Fig 13).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo and further with Wang with the molded electronic assembly further comprising a heat conductive material disposed on the substrate and surrounding the device pins to benefit from efficiently dissipating heat generated by the electronic components to the outside environment (Wang, Col 1, II. 14-19).
Regarding Claim 7, Syu in view of Otsubo and further in view of Wang discloses the limitations of Claim 6, however Syu as modified does not disclose wherein the heat conductive material and the circuit are coplanar.
Instead Wang (In Fig 13) further teaches wherein the heat conductive material (23) and the circuit (50, 51) are coplanar (Fig 13).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo and further with Wang with the heat conductive material and the circuit being coplanar to benefit from efficiently dissipating heat generated by the electronic components to the outside environment (Wang, Col 1, II. 14-19).
Regarding Claim 8, Syu in view of Otsubo and further in view of Wang discloses the limitations of Claim 6, however Syu as modified does not disclose wherein the heat conductive material covers at least one portion of the at least one patterned heat dissipation structure and covers at least one portion of the circuit.
Instead, Wang (In Fig 13) further teaches wherein the heat conductive material (23) covers at least one portion of the at least one patterned heat dissipation structure (33) and covers at least one portion of the circuit (51), (Fig 13).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo and further with Wang with the heat conductive material covering at least one portion of the at least one patterned heat dissipation structure and covering at least one portion of the circuit to benefit from efficiently dissipating heat generated by the electronic components to the outside environment (Wang, Col 1, II. 14-19).
Regarding Claim 9, Syu in view of Otsubo and further in view of Wang discloses the limitations of Claim 6, however Syu as modified does not disclose wherein the heat conductive material is located between the circuit and the top surface.
Instead Wang (In Fig 13) further teaches wherein the heat conductive material (23) is located between the circuit (50) and the top surface (top surface of 22), (Fig 13).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo and further with Wang with the heat conductive material being located between the circuit and the top surface to benefit from efficiently dissipating heat generated by the electronic components to the outside environment (Wang, Col 1, II. 14-19).
Claims 12 and 14 are rejected under 35 U.S.C. § 103 as being unpatentable over Syu in view of Otsubo and further in view of Dranchak et al (US 5,953,214).
Regarding Claim 12, Syu in view of Otsubo discloses the limitations of Claim 1, however Syu as modified does not disclose wherein each of the device pins of the electronic devices is electrically connected to a corresponding signal contact of the signal contacts through a conductive glue.
Instead, Dranchak (In Fig 3) teaches wherein each of the device pins (pins of 11), (Fig 3) of the electronic devices (11) is electrically connected to a corresponding signal contact (27) of the signal contacts (27) through a conductive glue (Col 4, II. 27-30), (Fig 3).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo and further with Dranchak with each of the device pins of the electronic devices being electrically connected to a corresponding signal contact of the signal contacts through a conductive glue to benefit from assuring effective repair, upgrade, and/or replacement of various components of the system (Dranchak, Col 1, II. 26-38).
Regarding Claim 14, Syu in view of Otsubo and further in view of Dranchak discloses the limitations of Claim 12, however Syu (In Fig 1E) further disclose wherein the at least one patterned heat dissipation structure (104) further extends to and surrounds a side of a corresponding device pin (310) of the device pins (310), (Fig 1E).
Claim 13 is rejected under 35 U.S.C. § 103 as being unpatentable over Syu in view of Otsubo further in view of Dranchak and further in view of Ha et al (US 2010/0244212).
Regarding Claim 13, Syu in view of Otsubo and further in view of Dranchak discloses the limitations of Claim 12, however Syu as modified does not disclose wherein the at least one patterned heat dissipation structure surrounds the corresponding conductive glue.
Instead, Ha (In Fig 1) teaches wherein the at least one patterned heat dissipation structure (124) surrounds the corresponding conductive glue (122), (¶ 95, II. 7-16).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo further with Dranchak and further with Ha with the at least one patterned heat dissipation structure surrounding the corresponding conductive glue to benefit from effectively dissipate heat from upper package, while preventing electrical short circuits between solder balls (Dranchak, ¶ 6, II. 1-8).
Claim 15 is rejected under 35 U.S.C. § 103 as being unpatentable over Syu in view of Otsubo and further in view of Ishida et al (UD2010/0328638).
Regarding Claim 13, Syu in view of Otsubo discloses the limitations of Claim 1, however Syu as modified does not disclose wherein a heat conductive coefficient of the at least one patterned heat dissipation structure is ≧6W/mK.
Instead, Ishida (In Fig 1) teaches wherein a heat conductive coefficient of the at least one patterned heat dissipation structure (5) is ≧6W/mK (¶ 47, II. 4-8).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Syu with Otsubo and further with Ishida with a heat conductive coefficient of the at least one patterned heat dissipation structure being ≧6W/mK to benefit from efficiently releasing the heat from the chip and transferring the heat to a heat sink through the adhesive (Ishida, ¶ 6, II. 1-6).
Examiner Note; It should be mentioned that; it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller 105 USPQ 233 (CCPA 1955).
Allowable Subject Matter
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to Claims 17-20, the allowability resides in the overall structure of the device as recited in independent Claim 17 and at least in part because Claim 17 recites, “a patterned heat dissipation structure, having a heat conductive coefficient ≧6W/mK and having a first transparent region; and a decorative layer, located on one side of the circuit substrate and having a second transparent region, wherein a region where the first transparent region is orthogonally projected on the substrate is overlapped with and greater than a region where the second transparent region is orthogonally projected on the substrate, and the region where the first transparent region is orthogonally projected on the substrate is not overlapped with a region where the electronic devices are orthogonally projected on the substrate”.
The aforementioned limitation in combination with all remaining limitations of Claim 17 are believed to render said Claim 17 and all Claims dependent therefrom (Claims 18-20) patentable over the art of record.
The closest art of record is believed to be that of Syu et al (2018/0082936 – hereafter “Syu”).
While Syu Fig 1E teaches a molded electronic assembly (10a), comprising: a circuit substrate (201/202/203/205), comprising a substrate (202) and a circuit (201/203/205), (Fig 1E), wherein the substrate (202) has a top surface (Fig 1E), the circuit (201/203/205) has a plurality of signal contacts (205), and the signal contacts (205) are distributed on the top surface (Fig 1E); a plurality of electronic devices (300), disposed on the circuit substrate (201/202/203/205), (Fig 1E), each of the electronic devices (300) having a plurality of device pins (310) connected to the signal contacts (205), (Fig 1E), however neither Syu nor any other art of record, either alone or in a combination, teach or suggest above-mentioned limitations of Claim 17.
Any comment considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submission should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure; Semiconductor Device and Method for Fabricating the Same US 2010/0148363, Circuit Board and Manufacturing Method Thereof US 2008/0101045, Substrate with Pin, Manufacturing Method Thereof, and Semiconductor Product US 2008/0296752, Semiconductor Package and Manufacturing Method Thereof US 2020/0357770, Circuit-Component-Containing Module US 2005/0051358. Other pertinent art made of record are on form PTO-892 notice of reference cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMIR JALALI whose telephone number is (303)297-4308. The examiner can normally be reached on Monday - Friday 8:30am - 5:00pm, Mountain Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached on 571-272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMIR A JALALI/Primary Examiner, Art Unit 2835