DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, and 4-7, are rejected under 35 U.S.C. 103 as being unpatentable over the US Patent Application Publication to Huang (20190004247US) in view of the US Patent Application Publication to Chang (2021/0096310US).
In terms of Claim 1, Huang teaches a method of producing a photonic package (Figure 1a-f), comprising: disposing a first wafer (See Figure 1e below: area in the bottom box) comprising a plurality of optical dies (Figure 1e below: area in the bottom box wherein adjacent dies located across the dotted line defined by area of 78; [0049]), extend over a carrier (Figure 1e: area of bottom box extend over 2), wherein each of the optical dies (Figure 1e: area of bottom box) comprise a front side (Figure 1e: top side of bottom box) and a back side opposite to the front side (Figure 1e: bottom side of bottom box), and wherein the front side of each of the optical dies face the carrier (Figure 1e below: wherein top side or front side of bottom box faces carrier 20 downward as depicted by dotted arrow point down towards 20); bonding the first wafer (Figure 1e: bottom box) to a second wafer (Figure 1e: top box) comprising a plurality of electronic dies (Figure 1e: 54 which is similar to 6 below wherein plurality of dies are present in each dotted line area of 10; [0040]) , wherein each of the electronic dies (54) comprise a front side (bottom side of 54) and a back side (top side of 54) opposite to the front side (Figure 1e: see front and back side of 54), and wherein the front side of each of the optical dies (top side of bottom box) face the back side of each of the electronic dies (Figure 1e below: see dotted arrow extending from top side of bottom box to top side of top box), respectively; removing the carrier from the first wafer (Figure 1f: wherein carrier 2 is remove; [0041]), and dividing the bonded first wafer and second wafer into a plurality of photonic packages ([0040-0041] and Figure 1e wherein each die package is cut or diced along dotted lines defining region 78 as shown in Figure 1a).
Huang does not teach wherein the front side of each of the electronic dies face the back side of each of the optical dies respectively.
Chang does teach wherein the front side of each of the electronic dies face the back side of each of the optical dies respectively ([0065]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the orientation of die to be stacked on top of each other in face to back configuration in order to reduce long wiring or conductor traces or vias. This reduces the heat and improves transmission efficiency but reducing the length of the transmission medium. Base on the orientation of the electrical lines one would be motivated to use face to back to optimize the coupling length of the transmission lines for the electronic package and improve power consumption.
As for Claim 2, Huang/ Chang teaches the method of Claim 1, further comprising forming at least one through-via (Figure 1a: 14/46) penetrating each of the optical dies (Figure 1a below: bottom box area) of the first wafer from the back side to the front side (Figure 1a: 14/44).
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As for Claim 4, Huang/ Chang teaches the method of Claim 1, further comprising forming a grating coupler (Figure 1a: 34) opening on the front side of each of the optical dies of the first wafer (Figure 1a: 34 and openings 52a and 52b).
As for Claim 5, Huang/ Chang teaches the method of Claim 1, wherein the bonding of the first wafer to the second wafer (Figure 1a: top and bottom box) further comprises: forming a first bonding structure over the back side (Figure 1a: 48 and 50) of each of the optical dies and a second bonding structure (Figure 1b: 56 and 58) over the front side of each of the electronic dies (Figure 1a: the top box and bottom box are flip-chip bonded meaning the top box is flip on top of bottom box; Figure 1a orientation of the top box once flip upside down the orientation of 56/58 will over the back side. This is similar to the 2 chip orientation as shown in Figure 6b of the applicant before bonding [See Figure 6b: 220 and 210] and after bonding [Figure 6c: at 220f and 210F]); and bonding the first bonding structure with the second bonding structure (Figure 1a: 48/50 is bonded to 56/58 in Figure 1b), wherein the first bonding structure (48/50) comprises a plurality of first conductive pads (Figure 1a: 50 or 48 are considered pads by the examiner) embedded in a first dielectric layer (46 or 49) and the second bonding structure (56/58) comprises a plurality of second conductive pads (56) embedded in a second dielectric layer (58 is a dielectric, although not disclosed it must inherently be a dielectric otherwise all the electrical connections with short with each other; hence rendering the device inoperable).
As for Claim 6, Huang/ Chang teaches the method of Claim 5, wherein bonding the first bonding structure (Figure 1a: 48/50) with the second bonding structure (56/58) comprises bonding the plurality of first conductive pads (48/50) with the plurality of second conductive pads (56), respectively (Figure 1a: 48/50 and Figure 1b: 50/56).
As for Claim 7, Huang/ Chang teaches the method of Claim 1, wherein the through-via (Figure 1a: 14/44) is coupled to at least one of the pluralities of the bonded first and second conductive pads (Figure 1a: 44 is coupled to 48).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over the US Patent Application Publication to Huang (2019/0004247US) in view of the US Patent Application Publication to Chang (2021/0096310US) as applied to claim 1 above, and further in view of the US Patent to Alapati (11,107,799US).
In regards to Claim 3, Huang teaches the method of Claim 2.
Huang does not teach thinning down the first wafer or optical die prior to forming the at least one through-via.
Alapati does teach wherein the PIC or EIC are thinned to obtain a thinner smaller form factor device along the heigh dimension (Column 9, lines 20-55).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the method of Huang wherein a thinning step is performed on the 1st wafer or the optical die in order to produce a thinner package (Alapati Column 9, lines 20-55), which will produce a smaller device footprint along the height dimension.
Huang / Alapati does not teach the thinning process is performed before the vias are formed.
However, the examiner considers this to be an obvious modification in view of KSR “obvious to try” rationale wherein the finite number of solutions are two choices. One can thin out the device before the via formation or after the via formation. The examiner considers the act of thinning out the desire thickness of the electronic die to be obvious because it would prevent debris from entering the via due the thinning / grinding or polishing act that is requires with thinning out the electronic die which may leads to blockage of unwanted debris in the through vias. It would have been obvious to one of ordinary skill in the art before the effective filing date of to modify the method of Huang / Liu to perform the thinning out process prior to forming the through via in order to prevent unwanted debris from entering the through via passageway and block the via during manufacturing (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421, 82 USPQ2d 1385, 1397 (2007)).
Claims 8, 15 and 22-24 are rejected under 35 U.S.C. 102a1 as being anticipated by the US Patent Application Publication to Huang (20190004247US) in view of the US Patent Application Publication to Chen (20210302654US).
In terms of Claim 8, Huang teaches a method of producing a photonic package (Figure 1a-f), comprising: providing a first wafer (Figure 1e: bottom box) comprising a plurality of optical dies (See Figure 1e above: bottom box, having multiple dies in area of Figure 1a: 78 along the wafer [0040-0041])), wherein each of the optical dies comprise a front side and a back side opposite to the front side (Figure 1e: front and back side of bottom box); bonding the first wafer to a second wafer (Figure 1e: bottom box bonded to top box) comprising a plurality of electronic dies (54; [0041]), wherein each of the electronic dies comprise a front side and a back side opposite to the front side (Figure 1e: above front and back side of electronic die), and wherein the front side of each of the optical dies face the front side of each of the electronic dies (See Figure 1e: front and back side of electronic die), respectively; forming a grating coupler opening (see area of 52a) penetrating through each of the electronic dies (see opening 52 penetrate through the top layer which the examiner considers as electronic die) and exposing the front side of each of the optical dies (see top surface of 40) of the first wafer (see bottom box area below); and dividing the bonded first wafer and second wafer into a plurality of photonic packages (Figure 1a: see area of 78).
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In regards to claim 15, Huang teaches a semiconductor package structure (Figure 1a-f) comprising: a first die (Figure 1e below: bottom box), comprising: a first die substrate (Figure 1e: 12); a first interconnect structure (Figure 1a: 50 or Figure 1e below: “interconnect structure’) over the first die substrate (Figure 1a: 38 is over 12); a first dielectric layer (Figure 1a: 46) over the first die substrate (Figure 46); and first conductive pads (Figure 1a: 48/50) embedded in the first dielectric layer (46); and a second die (Figure 1e: top box), comprising: a second die substrate (Figure 1e: 60 housing 54); a second interconnect structure (44) over the second die substrate (Figure 1a: the top box and bottom box are flip-chip bonded meaning the top box is flip on top of bottom box; Figure 1a orientation of the top box once flip upside down the orientation of 56/58 will be over substrate 60). This is similar to the 2 chip orientation as shown in Figure 6b of the applicant before bonding [See Figure 6b: 220 and 210] and after bonding [Figure 6c: at 220f and 210F]); a second dielectric layer (58) over the second die substrate (Figure 1e: 58 is over 60 in an upside down configuration, mainly portion 54 of substrate 60); and second conductive pads (Figure 1e: 56) embedded in the second dielectric layer (58 is a dielectric, although not disclosed it must be a dielectric otherwise all the electrical connections with short with each other, thus rendering the device inoperable); wherein the first dielectric layer (46) and the second dielectric layer (58), and the first conductive pads and the second conductive pads (48/50 and 56) are connected to each other respectively to form a bonding structure (Figure 1e: 48/50/56/58), and wherein one of the first die (Figure 1e: bottom box 12) and the second die (Figure 1e: bottom box containing an adjacent die contain 12) is an optical die (Figure 1e: bottom box is an optical die because it houses optical components such 34; ) and the other one of the first die (Figure 1e: top box containing 54) and second die (top box containing adjacent die 54) is an electronic die (Figure 1e: 78 contains an optical die and electronic die, a similar package adjacent contains the same optical and electronic die configurations).
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Huang does not teach a grating coupler opening penetrating the second die and the first dielectric layer.
Chen does teach a grating coupler opening (Figure 4: 40; [0014]) penetrating the second die and the first dielectric layer (See Figure 4 below; [0014]). It would have been obvious to one of ordinary skill in art before the effective filing date to modify the device of Huang wherein the opening goes through the dielectric layer of electronic die and optical in order to improve optical coupling from a fiber source similar to the one shown by Chen in Figure 2a, the opening being place through the dielectric allows for the fiber or coupling distant to be reduce thus improved coupling performances ([0014]).
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As for claims 22, Huang / Chen teaches the device of claim 15, wherein Huang teaches the first conductive pads are bonded to an aligned with the second conductive pads (48/50 and 58/56).
As for claims 23, Huang / Chen teaches the device of claim 15, wherein the first conductive pads and the second pads comprises metal or metal alloy (]0024-0027]).
As for claims 24, Huang / Chen teaches the device of claim 22, wherein at least one of the bonded first conductive pads (56 to 50) and second conductive pad is physically connected to the second interconnect structure (Figure 1e: 48/50)
Claims 9, 10, 12-14, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication to Huang (2019/0004247US) / Chen 20210302654US as applied to claims 8 and 15 above, and further in view of US Patent Application Publication to Liu 2021/0166991US.
In regards to Claims 9, and 19-20, Huang teaches the method of claim 8 and the device of claim 15; wherein a grating coupler is located on the 1st substrate (Figure 1a: 34 and 12).
Huang does not teach the method further comprising forming at least one through-via penetrating each of the electronic dies of the second wafer from the back side to the front side; and comprising a through-via penetrating the second die structure and physically connecting the second interconnect structure.
Liu does teach a method of making a photonic chip (Figure 5: see below wherein through via (Through Silicon Vias or TSV) extend through the layer housing the electronic device (Figure 5: electronic die) further comprising forming at least one through-via penetrating each of the electronic die (electronic die) of the second wafer from the back side to the front side (Figure 5: 2nd wafer or 2nd layer); and comprising a through-via penetrating (Figure 5: TSV) the second die (Figure 5: electronic die) structure and physically connecting the second interconnect structure (Figure 5: below interconnect layer between each dies).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the TSV at 44 to extend through the electronic die in order to stack additional dies such as other photonic or electronic dies for large scale applications to support more connections.
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Regarding claim 10 and 21, Huang / Chen / Liu teaches the method of Claim 9, wherein Huang teaches further comprising thinning down the second wafer ([0066]) wherein the grating coupler opening is formed after the thinning down the second wafer (See Figure 1e: wherein the opening requires 52a and 66a to have thickness predetermined before they are stacked on top of each to form the opening area of 52a/66a).
Huang / Chen and Liu do not teach thinning prior to forming the at least one through-via.
However, the examiner considers this to be an obvious modification in view of KSR “obvious to try” rationale wherein the finite number of solutions are two choices. One can thin out the device before the via formation or after the via formation. The examiner considers the act of thinning out the desire thickness of the electronic die to be obvious because it would prevent debris from entering the via due the thinning / grinding or polishing act that is requires with thinning out the electronic die which may leads to blockage of unwanted debris in the through vias. It would have been obvious to one of ordinary skill in the art before the effective filing date of to modify the method of Huang / Liu to perform the thinning out process prior to forming the through via in order to prevent unwanted debris from entering the through via passageway and block the via during manufacturing (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 421, 82 USPQ2d 1385, 1397 (2007)).
In regards to claim 12, Huang / Chen / Liu teaches the method of claim 9, wherein Huang teaches wherein the bonding of the first wafer (Figure 1e: bottom box) to the second wafer (Figure 1e: top box) further comprises: forming a first bonding structure over the front side of each of the optical dies (Figure 1a: 48 and 50 over top side of bottom box shown in Figure 1e) and a second bonding structure (Figure 1b: 56/58) over the front side of each of the electronic dies (Figure 1a: the top box and bottom box are flip-chip bonded meaning the top box is flip on top of bottom box; Figure 1a orientation of the top box once flip upside down the orientation of 56/58 will over the back side. This is similar to the 2 chip orientation as shown in Figure 6b of the applicant before bonding [See Figure 6b: 220 and 210] and after bonding [Figure 6c: at 220f and 210F]); and bonding the first bonding structure (Figure 1a: 48/50) with the second bonding structure (Figure 1b: 58/56), wherein the first bonding structure comprises a plurality of first conductive interconnect (Figure 1a: 48 or 50 are pads) embedded in a first dielectric layer (Figure 1a: 46 or 49) and the second bonding structure (Figure 1b: 56/ 58) comprises a plurality of second conductive pads (56) embedded in a second dielectric layer (58 is a dielectric, although not disclosed it must be a dielectric otherwise all the electrical connections with short with each other, thus rendering the device inoperable).
In regards to claim 13, Huang / Chen / Liu teaches the method of claim 12, wherein Huang teaches wherein bonding the first bonding structure (Figure 1a: 48/50) with the second bonding structure (Figure 1b: 56/58) comprises bonding the plurality of first conductive pads (48 or 50) with the plurality of second conductive pads (56), respectively (via 58).
In regards to claim 14, Huang / Chen/ Liu teaches the method of claim 13, wherein Huang teaches wherein the through-via (44/14) is coupled to at least one of the pluralities of the bonded first and second conductive pads (Figure 1a: 44 is coupled 48/50 which is coupled to 56).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on any of the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly amended Claim 1 have been rejected in view of newly cited prior art to Chang as detail above.
Newly amended Claim 8 and 15 have been rejected in view of the prior art to Chen as detailed above.
Newly added claims 21-24 are also rejected as detailed above.
This action is therefore made FINAL for the reasons cited above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOANG Q TRAN whose telephone number is (571)272-5049. The examiner can normally be reached 9:30 am - 5:30pm Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 5712722397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HOANG Q TRAN/Examiner, Art Unit 2874
/UYEN CHAU N LE/Supervisory Patent Examiner, Art Unit 2874
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