DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Election/Restrictions
Applicant’s election of claims 1-17 in the reply filed on April 17th, 2026, is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Therefore, claims 18-20 are hereby withdrawn from consideration pursuant to 37 CFR 1.142 (b).
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 and/or 103 rejections are provided in parenthesis.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “100” has been used to designate both the semiconductor package of fig. 1 and the semiconductor package of fig. 2 despite these packages constituting distinct embodiments of the instant invention. The semiconductor package shown in fig. 2 (i.e. wherein the bridge die is bonded to the first and second dies via hybrid bonding) should be designated with a different reference character such as “100a” or “200” to delineate the different embodiments.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Examiner respectfully requests that applicant also update the instant Specification to reflect the requested changes (e.g. in instant paragraph [0060]-[0062]) in order to overcome this objection.
Specification
The abstract of the disclosure is objected to because of a syntactical error in line 7: lines 6-8 should be changed to: “and a molding material disposed on the redistribution layer structure die”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claim 7 is objected to because of the following informalities: the claim recites “wherein the bridge die includes a memory semiconductor” but should be changed to recite “wherein the bridge die includes a memory semiconductor chip” (in accordance with instant paragraph [0057]). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, and 8-9, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 20170373037 A1), hereinafter referred to as “Yu”.
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Regarding claim 1, Yu discloses A semiconductor package (fig. 9, 100; [0033]; note that the embodiment of fig. 8 is substantially the same as that of fig. 9, the only difference being that memory devices 130a have different architectures than memory devices 130), comprising:
a redistribution layer structure (fig. 9, 150; see [0023]);
a first semiconductor die (fig. 9, left 130a; see [0033]) and a second semiconductor die (fig. 9, right 130a; see [0033]) disposed on the redistribution layer structure;
a bridge die (fig. 9, 110; c.f. fig. 8; see [0013]) disposed on the first semiconductor die and the second semiconductor die and that electrically connects the first semiconductor die and the second semiconductor die to each other (see fig. 9 (c.f. fig. 8) and [0025]: if the redistribution circuit structure is electrically connected to both IC 110 and memory devices 130(a), then both of the memory devices 130a (as shown in fig. 9) must be electrically connected to each other by IC 110);
and a molding material (fig. 9, 140; see [0021]) that molds the first semiconductor die, the second semiconductor die, and the bridge die onto the redistribution layer structure (see [0021]: memory devices 130 (and, thus, memory devices 130a) and IC 110 are embedded in insulating encapsulation 140; see fig. 9: insulating encapsulation 140 molds devices 130a and IC 110 onto redistribution circuit structure 150),
wherein a bottom surface of the first semiconductor die and a bottom surface of the second semiconductor die are coplanar with an upper surface of the redistribution layer structure (see fig. 9).
Regarding claim 3, Yu discloses the semiconductor package of claim 1, wherein the bridge die (fig. 9, 110; c.f. fig. 8) is disposed on a part of an upper surface of the first semiconductor die (fig. 9, left 130a) and a part of an upper surface of the second semiconductor die (fig. 9, right 130a).
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Regarding claim 8, Yu discloses a semiconductor package (fig. 9, 100; [0033]), comprising:
a redistribution layer structure (fig. 9, 150; see [0023]);
a first semiconductor die (fig. 9, left 130a; see [0033]) and a second semiconductor die (fig. 9, right 130a; see [0033]) disposed on the redistribution layer structure;
an interconnection structure (see fig. 9, c.f. fig. 8; see [0017]: memory devices 130 (and 130a as described in [0033]) are mounted on IC 110 “through flip-chip bonding and underfill processes”; the interconnection structure comprises micro-bumps 134a and surrounding (unlabeled) underfill material) disposed on the first semiconductor die and the second semiconductor die;
a bridge die (fig. 9, 110; c.f. fig. 8; see [0013]) disposed on the interconnection structure, wherein the interconnection structure electrically connects the bridge die and the first semiconductor die and the bridge die and the second semiconductor die (see [0017]), and the bridge die electrically connects the first semiconductor die and the second semiconductor die to each other (see fig. 9 (c.f. fig. 8) and [0025]: if the redistribution circuit structure is electrically connected to both IC 110 and memory devices 130(a), then both of the memory devices 130a (as shown in fig. 9) must be electrically connected to each other by IC 110);
and a molding material (fig. 9, 140; see [0021]) disposed on the redistribution layer structure and that molds the first semiconductor die, the second semiconductor die, and the bridge die (see [0021]: memory devices 130 (and, thus, memory devices 130a) and IC 110 are embedded in insulating encapsulation 140; see fig. 9: insulating encapsulation 140 molds devices 130a and IC 110 onto redistribution circuit structure 150),
wherein bottom surfaces of the first semiconductor die and the second semiconductor die are coplanar with an upper surface of the redistribution layer structure (see fig. 9).
Regarding claim 9, Yu discloses the semiconductor package of claim 8, wherein the interconnection structure (see fig. 9, c.f. fig. 8; see [0017]: the interconnection structure comprises micro-bumps 134a and surrounding (unlabeled) underfill material) includes a micro bump (fig. 9, 134a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Chen et al. (US 20190148276 A1), hereinafter referred to as “Chen”.
Yu discloses the semiconductor package of claim 1.
Yu fails to explicitly disclose wherein the first semiconductor die and the second semiconductor die exchange signals through the bridge die.
Chen discloses a semiconductor package (Chen fig. 14, 602; see [0010]), wherein a first semiconductor die (Chen fig. 14, left 114 within package region 602; see [0017]) and a second semiconductor die (Chen fig. 14, right 114 within package region 602; see [0017]) exchange signals through a bridge die (Chen fig. 14, 160; see [0022]; see [0024]: “the routing die 160 … is used for routing signals between integrated circuit dies 114”).
The signal exchange teachings of Chen are applied to the bridge die of the device of Yu wherein the combination discloses wherein the first semiconductor die and the second semiconductor die exchange signals through the bridge die.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yu with the signal exchange techniques of Chen because the benefits of signal exchange between dies in semiconductor packages are well known in the art (e.g. see Yu [0068] and note the stated goal of providing a short signal transmission path between IC 110 and memory devices 130(a); communication between various dies in a semiconductor package is essential for power efficiency and the overall effectiveness of the device).
Regarding claim 5, Yu discloses the semiconductor package of claim 1, comprising a redistribution layer structure (Yu fig. 9, 150; see [0023]).
Yu fails to explicitly disclose wherein: the redistribution layer structure includes a plurality of redistribution vias, and an uppermost width of each redistribution via of the plurality of redistribution vias is less than a lowermost width thereof.
Chen discloses a semiconductor package (Chen fig. 14, 602; see [0010]), wherein: a redistribution layer structure (Chen fig. 14, 131; see [0032]-[0036]) includes a plurality of redistribution vias (see Chen fig. 10, 134; see [0035] for a description of redistribution via formation),
and an uppermost width of each redistribution via of the plurality of redistribution vias is less than a lowermost width thereof (see Chen fig. 14; c.f. fig. 10; the uppermost width of each via of the various metallization patterns 134, 138, and 142 (see fig. 10), is less than the respective lowermost width).
The redistribution layer structure of Chen is incorporated as the redistribution layer structure of the device of Yu wherein the combination discloses all of the limitations of claim 5.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yu with the redistribution layer structure of Chen because the combination is a simple substitution of one know element for another to obtain predictable results—simple substitution of the redistribution layer structure of Yu (Yu fig. 9, 150) with the redistribution layer structure of Chen (Chen fig. 14, 131) to obtain predictable results (reduced manufacturing complexity and predictable electrical coupling; the use of redistribution layers with via holes is well known in the packaging art).
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Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Chen, further in view of Shih et al. (US 20170365580 A1), hereinafter referred to as “Shih”, further in view of Choi (US 20200294889 A1), hereinafter referred to as “Choi”.
Yu discloses the semiconductor package of claim 1, comprising a redistribution layer structure (Yu fig. 9, 150; see [0023]).
Yu fails to explicitly disclose wherein: the redistribution layer structure includes a plurality of redistribution vias, the first semiconductor die and the second semiconductor die each include a plurality of connection pads at a lowest level, and each redistribution via of an uppermost level of the plurality of redistribution vias is directly bonded with a corresponding connection pad of the plurality of connection pads.
Chen discloses a semiconductor package (Chen fig. 14, 602; see [0010]), wherein: a redistribution layer structure (Chen fig. 14, 131; see [0032]-[0036]) includes a plurality of redistribution vias (see Chen fig. 10, 134; see [0035] for a description of redistribution via formation).
The redistribution layer structure of Chen is incorporated as the redistribution layer structure of the device of Yu wherein the combination discloses wherein: the redistribution layer structure includes a plurality of redistribution vias.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yu with the redistribution layer structure of Chen because the combination is a simple substitution of one know element for another to obtain predictable results—simple substitution of the redistribution layer structure of Yu (Yu fig. 9, 150) with the redistribution layer structure of Chen (Chen fig. 14, 131) to obtain predictable results (reduced manufacturing complexity and predictable electrical coupling; the use of redistribution layers with via holes is well known in the packaging art).
Shih discloses a semiconductor package (Shih fig. 13, 4; see [0050]), wherein a first semiconductor die (Shih fig. 13, 11 (c.f. fig. 9); see [0042]) and a second semiconductor die (Shih fig. 13, 12 (c.f. fig. 9); see [0042]) each include a plurality of connection pads (Shih fig. 13, 111 and 121; see [0043]) at a lowest level (see Shih fig. 13).
The connection pads of Shih are incorporated into the first and second semiconductor dies of the device of Yu wherein the combination discloses wherein the first semiconductor die and the second semiconductor die each include a plurality of connection pads at a lowest level.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yu with the connection pads of Shih to reduce the contact resistance between the first/second semiconductor dies and the redistribution layer structure.
Choi discloses a semiconductor package (Choi fig. 1, 10; see [0021]; see [0027] and note that fig. 2 shows the RDLs underlying and connecting the semiconductor dies 100 and 200) comprising a first semiconductor die (Choi fig. 1, 100; see [0021]) having a plurality of connection pads (Choi fig. 2: 110, 120, 130; c.f. fig. 19), wherein each redistribution via of an uppermost level of a plurality of redistribution vias (Choi fig. 2: 310, 320, 340; c.f. fig. 1; see [0026] and [0030]) is directly bonded with a corresponding connection pad of the plurality of connection pads (see fig. 2; each RDL shown in fig. 2 is directly bonded (see fig. 1) to a corresponding connection pad of the plurality of connection pads included in first semiconductor die 100).
The connection pad and redistribution teachings of Choi are applied to the previously combined device of Yu and Shih (applied to the first and second semiconductor dies) wherein the present combination discloses wherein each redistribution via of an uppermost level of the plurality of redistribution vias is directly bonded with a corresponding connection pad of the plurality of connection pads.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Yu and Shih with the connection and redistribution teachings of Choi to reduce power noise (see Choi [0031]). The modification would also improve signal integrity and increase connectivity in the device.
Claims 6-7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Shih.
Regarding claim 6, Yu discloses the semiconductor package of claim 1.
Yu fails to explicitly disclose wherein the first semiconductor die and the second semiconductor die each include an application processor (AP).
Shih discloses a semiconductor package (Shih fig. 13, 4; see [0050]), wherein a first semiconductor die (Shih fig. 13, 11; see [0042]) and a second semiconductor die (Shih fig. 13, 12; see [0042]) each include an application processor (AP) (see Shih [0042]).
The first and second semiconductor dies of Shih are incorporated as the first and second semiconductor dies of the device of Yu wherein the combination discloses wherein the first semiconductor die and the second semiconductor die each include an application processor (AP).
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yu with the semiconductor dies of Shih to increase the application processing power of the device (the benefit of increased processing power for semiconductor packages is well-known in the art).
Regarding claim 7 (applicant is reminded of the objection to claim 7 entered above), Yu discloses the semiconductor package of claim 1,
Yu fails to explicitly disclose wherein the bridge die includes a memory semiconductor chip.
Shih discloses a semiconductor package (Shih fig. 13, 4; see [0050]), wherein a bridge die (Shih fig. 13, 13) includes a memory semiconductor chip (see [0051]: bridge memory die 13 is a dual-port DRAM chip).
The bridge memory die of Shih is incorporated as the bridge die of the device of Yu wherein the combination discloses wherein the bridge die includes a memory semiconductor chip.
It would have been obvious for one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yu with the bridge memory die of Shih to allow inter-processor communication between the first and second semiconductor dies and significantly increase operating speeds (see Shih [0051]). The combination would also increase memory storage for the device.
Regarding claim 17, Yu discloses the semiconductor package of claim 8,
Yu fails to disclose wherein: the first semiconductor die and the second semiconductor die each include a plurality of through silicon vias (TSVs), respectively, and the plurality of through silicon vias electrically connect the interconnection structure and the redistribution layer structure.
Shih discloses a semiconductor package (Shih fig. 13, 4; see [0050]), wherein a first semiconductor die (Shih fig. 13, 11; see [0042]) and a second semiconductor die (Shih fig. 13, 12; see [0042]) each include a plurality of through silicon vias (TSVs) (Shih fig. 13, 116 and 126), respectively, and the plurality of through silicon vias electrically connect an interconnection structure (Shih fig. 13, 133; see [0045]) and a redistribution layer structure (Shih fig. 13, 30; c.f. fig. 12; see [0041]; see [0044] and note that TSVs 116 and 126 are electrically coupled to at least some of the I/O pads 111 and 121, respectively; see fig. 13 and [0043] and note that I/O pads 111 and 121 are connected to the RDL 30 through connecting elements 113 and 123 respectively; see [0045] and note that TSVs 116 and 126 are electrically connected to connecting elements 133).
The TSVs of Shih are incorporated into the first and second semiconductor dies of the device of Yu wherein the combination discloses wherein: the first semiconductor die and the second semiconductor die each include a plurality of through silicon vias (TSVs), respectively, and the plurality of through silicon vias electrically connect the interconnection structure and the redistribution layer structure.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yu with the TSVs of Shih to improve device connectivity while reducing space constraints. The TSVs would also serve to reduce unintended electrical resistance within the device.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Elsherbini et al. (US 20200091128 A1), hereinafter referred to as “Elsherbini”.
Regarding claim 10, Yu discloses the semiconductor package of claim 9.
Yu fails to explicitly disclose wherein the interconnection structure includes an insulating member that surrounds the micro bump.
Elsherbini discloses a semiconductor package (Elsherbini fig. 1A, 100) with an interconnection structure (see Elsherbini fig. 1A: the interconnection structure comprises die-to-die interconnects 130 and underfill material 127) that connects a plurality of semiconductor dies (Elsherbini fig. 1A: 114-3, 114-5, 114-6; see [0045]) with a bridge die (Elsherbini fig. 1A, 114-2; see [0045]), wherein the interconnection structure includes an insulating member (Elsherbini fig. 1A, 127; see [0035]) that surrounds a micro bump (Elsherbini fig. 1A, 130; see [0037]).
The insulating member of Elsherbini is incorporated as the unlabeled underfill material of the device of Yu wherein the combination discloses wherein the interconnection structure includes an insulating member that surrounds the micro bump.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yu with the insulating member of Elsherbini to mitigate the effects of uneven thermal expansion in the combined device (e.g. see Elsherbini [0035]).
Regarding claim 11, the combined device of Yu and Elsherbini discloses the semiconductor package of claim 10, wherein the insulating member (Elsherbini fig. 1A, 127; incorporated as the unlabeled underfill material in the combined device) includes a molded under-fill (MUF) (see Elsherbini [0035]: “the underfill material 127 may include a … molded underfill”).
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Chen et al. (US 20230095134 A1), hereinafter referred to as “Chen2” (note that Chen2 qualifies as prior art under 35 U.S.C. 102(a)(2)).
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Regarding claim 12, Yu discloses the semiconductor package of claim 8.
Yu fails to explicitly disclose wherein the interconnection structure includes: a plurality of first bonding pads and a first insulation layer disposed on upper surfaces of the first semiconductor die and the second semiconductor die; and a plurality of second bonding pads and a second insulation layer disposed on a bottom surface of the bridge die.
Chen2 discloses a semiconductor package (Chen2 fig. 20, 50) comprising a bridge die (Chen2 fig. 23, 305; see [0022]) connected to a first semiconductor die (Chen2 fig. 23, 105b; see [0021]) and a second semiconductor die (Chen2 fig. 23, 105a; see [0021]) through an interconnection structure (see Chen2 fig. 23 and [0069]-[0070]; the interconnection structure is located between bridge die 305 and device dies 105a and 105b and comprises bond pads 20 and 354 along with bonding layer 18 and 352), wherein the interconnection structure includes: a plurality of first bonding pads (Chen2 fig. 20, 20 (i.e. 20b, 20d); see [0064]) and a first insulation layer (Chen2 fig. 20, 18; see [0064]) disposed on upper surfaces of the first semiconductor die and the second semiconductor die; and a plurality of second bonding pads (Chen2 fig. 20, 354 (i.e. 354b, 354d); see [0055]) and a second insulation layer (Chen2 fig. 20, 352; see [0055]) disposed on a bottom surface of the bridge die.
The interconnection structure of Chen2 is incorporated as the interconnection structure of the device of Yu wherein the combination discloses wherein the interconnection structure includes: a plurality of first bonding pads and a first insulation layer disposed on upper surfaces of the first semiconductor die and the second semiconductor die; and a plurality of second bonding pads and a second insulation layer disposed on a bottom surface of the bridge die.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Yu with the interconnection structure of Chen2 to reduce energy consumption, provide less contact resistance, and provide higher frequency through-put than bridge devices utilizing bump connectors (see Chen2 [0072]);
and the combination is a simple substitution of one known element for another to obtain predictable results—simple substitution of the interconnection structure of Yu (see fig. 9, c.f. fig. 8; see [0017]: the interconnection structure of Yu comprises micro-bumps 134a and surrounding (unlabeled) underfill material) with the interconnection structure of Chen2 to obtain predictable results (see Chen2 [0072]).
Regarding claim 13, Yu and Chen2 disclose the semiconductor package of claim 12, wherein each first bonding pad (Chen2 fig. 20, 20b) of the plurality of first bonding pads (Chen2 fig. 20, 20 (i.e. 20b, 20d); see [0064]) is directly bonded to a corresponding second bonding pad (Chen2 fig. 20, 354b) of the plurality of second bonding pads (Chen2 fig. 20, 354 (i.e. 354b, 354d); see [0055]; see fig. 20 and [0069]: note that each first bonding pad is directly bonded to each second bonding pad).
Regarding claim 14, Yu and Chen2 disclose the semiconductor package of claim 13, wherein the first bonding pad (Chen2 fig. 20, 20b) and the second bonding pad (Chen2 fig. 20, 354b) each include copper (see Chen2 [0069]: since the metal-to-metal bonding between bond pads 20 and 354 is copper-to-copper direct bonding, both bond pads 20 and 354 must include copper).
Regarding claim 15, Yu and Chen2 disclose the semiconductor package of claim 12, wherein the first insulation layer (Chen2 fig. 20, 18; see [0064]) is directly bonded with the second insulation layer (Chen2 fig. 20, 352; see [0055]; see [0069]: bonding layer 18 is directly bonded with bonding layer 352 through fusion bonding).
Regarding claim 16, Yu and Chen2 disclose the semiconductor package of claim 15, wherein the first insulation layer (Chen2 fig. 20, 18; see [0064]) and the second insulation layer (Chen2 fig. 20, 352; see [0055]) each include at least one of a silicon oxide, a silicon nitride, or a silicon oxynitride (see Chen2 [0064]: bonding layer 18 includes silicon nitride; see [0055]: since “the processes and materials used to form the various features of the bridge dies 305 may be similar to the processes and materials used to form their like features in device die 105” and that bonding layer 352 is bonded to bonding layer 18 through fusion bonding, it follows that bonding layer 352 is composed of the same material as bonding layer 18).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNER F COLLINS whose telephone number is (571)272-5187. The examiner can normally be reached M-F, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at (571)272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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